最新免费av在线观看,亚洲综合一区成人在线,中文字幕精品无码一区二区三区,中文人妻av高清一区二区,中文字幕乱偷无码av先锋

ISL5216KI-1Z Datasheet

  • ISL5216KI-1Z

  • Four-Channel Programmable Digital DownConverter

  • 1095.01KB

  • 65頁

  • INTERSIL   INTERSIL

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

ISL5216
Serial Data Output Formatter Section
TO / FROM
OTHER CHANNELS
&
FIXED
TO
FLOAT
M
U
X
ROUND
&
SEQUENCER
1
DELAY
ZERO
PARALLEL
TO
SERIAL
&
& O
& R
&
SD2x
& O
& R
&
M
U
X
PARALLEL
TO
SERIAL
& O
& R
&
SD1x
OUTPUT SECTION
ZERO
I1
Q1
MAG
PHASE
I2
Q2
GAIN
STROBE
R
E
G
SYNC
GEN
SYNCx
M
U
X
ROUND
SEQUENCER
2
M
U
X
16
TO
碌P
INTERFACE
NOTE: Each serial output has 7 time slots. Each slot can contain I1, Q1, I2, Q2, Mag, phase or d蠁/dt, AGC gain, or zeros. Each slot can be 4, 6, 8,
10, 12, 16, 20, 24, or 32 (24 + 8 zeros) bits or disabled. Output 1 can also be 32-bit floating point. Slots can be disabled. A disabled slot will be one
clock wide if there are other active slots following. A sync can be asserted with any or all slots in output 1. The serial output can be delayed from 0
to 4095 serial clock periods from the input strobe. The serial outputs are always MSB first. The sync position applies to all time slots and can be one
clock prior to the first data bit, aligned with the first data bit, or one clock after the last data bit.
Serial Data Output Control Register
The serial data output control register contains sync position
and polarity (SYNCA, B, C or D), channel multiplexing, and
scaling controls for the SD1x and SD2x (x = A, B, C or D)
serial outputs (see Microprocessor Interface Section, IWA
register *014h).
Channel Routing Mask
The multiplexing mask bits for each channel (see
Microprocessor Interface Section, IWA register *014h bits
19:16 for SD1x or bits 15:12 for SD2x) can be used to enable
that channel鈥檚 output to any of the four serial outputs. These
bits control the AND gates that mask off the channels, so a
zero disables the channel鈥檚 connection to that output.
To configure more than one channel's output onto a serial
data output, the SD1 serial outputs and syncs from each
channel (0,1, 2 and 3) are brought to each of the SD1 serial
output sections and the SD2 serial outputs are brought to
28
each of the SD2 serial output sections (the syncs are only
associated with the SD1 serial outputs). There, the four
outputs are AND-ed with the multiplexing mask programmed
in the serial data output control registers of channels 0 thru 3
and OR-ed together. By gating off the channels that are not
wanted and delaying the data from each desired channel
appropriately, the channels can be multiplexed into a
common serial output stream. It should be noted that in
order to multiplex multiple channels onto a single serial data
stream the channels to be multiplexed must be synchronous.
Serial Data Output Time Slot Content/Format
Registers
These four registers are used to program the content and
format of the serial data output sequence time slots (see
Microprocessor Interface Section, IWA registers *015h -
*018h). There are seven data time slots that make up a serial
data output stream. The number of data bits and data format
July 8, 2005

ISL5216KI-1Z 產(chǎn)品屬性

  • Intersil

  • + 85 C

  • BGA

  • - 40 C

  • Tray

ISL5216KI-1Z相關(guān)型號(hào)PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號(hào)推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！