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ISL5217 Datasheet

  • ISL5217

  • Quad Programmable Up Converter

  • 43頁(yè)

  • INTERSIL   INTERSIL

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ISL5217
Gain Control
The gain control is implemented through a scaling multiplier
followed by a scaling shift. The combination of the multiplier
and shifter provide the final output gain of the channel. Gain
adjustment can vary from -0.0026 to -144 dBFS.
Given a desired attenuation, the scaling multiplier value,
Gain
MULT
(11:0) can be calculated by the following equation.
Gain
MULT
(11:0) = INT [10
|(Gain(db)| / 20 )
2
12
]
where INT[X] is the integer part of the real number X.
Table 5 details a few scaling multiplier values and their
associated attenuations.
TABLE 5. SCALING GAIN ATTENUATION
GAIN
MULT
(0xa, 11:0)
1111 1111 1111
1000 0000 0000
0100 0000 0000
0010 0000 0000
0001 0000 0000
0000 1000 0000
0000 0100 0000
0000 0010 0000
0000 0001 0000
0000 0000 1000
0000 0000 0100
0000 0000 0010
0000 0000 0001
GAIN (dBFS)
-0.0026
-6.021
-12.041
-18.062
-24.082
-30.103
-36.124
-42.144
-48.165
-54.186
-60.205
-66.226
-72.247
SCALING GAIN
(V
OUT
/V
IN
)%
99.97
50.0
25.0
12.5
6.25
3.125
1.5625
0.78125
0.39062
0.19531
0.097656
0.04828
0.02441
Sampling NCO
The Sample Rate NCO provides the SAMPLE CLK and
sample clock phase information to the data input FIFO鈥檚,
the shaping filters and the interpolation filters. The input
sample rate is set by the sample clock. The sample clock is
the MSB of the NCO accumulator and controls the
movement of sample data from the user to the shaping
filters. The coarse phase of the NCO accumulator controls
the processing of the shaping filter at 4x, 8x, or 16x the
sample clock rate. The fine phase of the NCO accumulator
controls the processing of the interpolation filter as it re-
samples the data from the shaping filter to the clock rate.
The block diagram is shown in Figure 11.
The sample frequency, SF, is set with 48-bit resolution. The
LSB is f
CLK
/2
48
. The internal accumulator resolution is 48
bits. Given a desired sample frequency, f
s,
the value for
SF(47:0) can be calculated by the following equation.
SF (47:0) = INT [(f
s
/ f
CLK
) * 2
48
]
The sample frequency, SF(47:0) is loaded 16 bits at a time
into Control Words 4, 5, and 6.
0x4, bits 15:0 = SF (47:32)
0x5, bits 15:0 = SF (31:16)
0x6, bits 15:0 = SF (15:0)
The output of the phase accumulator can be offset by phase
increments of 90 degrees without affecting the operation of
the phase accumulator. The desired offset increment is
loaded into FIR Control (0xd, bits 11:10).
Since it is not possible to represent all frequencies exactly
with an NCO, the phase accumulator length has been
extended to minimize the effect of phase error accumulation.
At an update rate of 1MHz, half an LSB of error in loading
the 48-bit accumulator is 1.8e-9. The accumulated phase
error after 1 year is 0.056 of a bit.
Given a desired attenuation, the shifting value Gain
SHIFT
(2:0) can be determined by a table look-up. Refer to Table 6.
TABLE 6. GAIN SHIFT VALUES
GAIN
SHIFT
(2:0)
000
001
010
011
100
101
110
111
GAIN (dBFS)
-72.247
-48.165
-30.103
-24.082
-18.062
-12.041
-6.021
0
SCALE
BY
4096
256
32
16
8
4
2
1
SCALING GAIN
(V
OUT
/V
IN
)%
0.02441
0.39062
3.125
6.25
12.5
25.0
50.0
100.0
Leap Counter
In addition to lengthening the NCO accumulator, a 32-bit
counter is available for realizing fixed integer interpolation
rates. The carry-out of the fixed integer counter can be used
to clear the coarse and/or fine phase of the sample rate
NCO. The fixed integer counter also provides a precarry-out
that can be used to synchronize fixed integer counters in
other devices. The fixed integer counter is enabled by FIR
Control (0xd, bit 12).
In programming the FID to clear the NCO accumulator,
consideration must be provided to ensure that FID is
programmed to clear the Error term only when the desired
error term should have been zero with an integer multiple of
the symbol rate. Selecting GSM as an example, the FID
should clear the NCO accumulator every third multiple of the
symbol rate or every 270833.333 * 3 sample clocks, as the
error term should only be zeroed during integer multiples of
The gain control is loaded into Control Word 0xa.
0xa, bits 14:12 = Gain
SHIFT
(2:0)
0xa, bits 11:0 = Gain
MULT
(11:0)
12

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