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ISL5239 Datasheet

  • ISL5239

  • Pre-Distortion Linearizer

  • 652.00KB

  • 31頁

  • INTERSIL   INTERSIL

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ISL5239
AC Electrical Specifications
Hold Time SERIN from CLK (Note 7)
Delay Time from CLK to TRIGOUT
Setup Time from TRIGIN to CLK
Hold Time TRIGIN from CLK
Setup Time from TMS and TDI to TCK
Hold Time TMS and TDI from TCK
Delay Time from TCK to TDO valid
Test Clock Frequency
Output Rise/Fall Time (Note 7)
NOTES:
6. AC tests performed with C
L
= 70pF. Input reference level for CLK is 1.5V, all other inputs 1.5V.
Test V
IH
= 3.0V, V
IHC
= 3.0V, V
IL
= 0V, V
OL
= 1.5V, V
OH
= 1.5V.
7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
8. Can be asynchronous to CLK, specification guarantying which CLK edge the device comes out of reset on.
9. Can be asynchronous to CLK, specification guarantying which CLK edge the device begins the read cycle on.
V
CCC
= 1.8鹵 5%, V
CCIO
= 3.3 鹵 5%, T
A
= -40
o
C to 85
o
C (Note 6)
(Continued)
SYMBOL
t
DHS
t
PDC
t
DS1
t
DH1
t
TS
t
TH
t
TD
f
T
t
RF
-
MIN
1
2 (Note 7)
2
2
3
3
8
50
3
7
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
MHz
ns
PARAMETER
AC Test Load Circuit
DUT
S
1
C
L
鈥?/div>
鹵
SWITCH S
1
OPEN FOR I
CCSB
AND I
CCOP
I
OH
1.5V
I
OL
鈥?/div>
TEST HEAD CAPACITANCE
EQUIVALENT CIRCUIT
Waveforms
CLK
t
SC1,
t
SCN
t
CLK
t
CH
t
CL
t
CLK
= 1 / F
CLK
SERCLK
t
SD1
SERSYNC
t
SD2
t
RH
t
RPW
RESET
SERIN
t
RS
SEROUT
t
DSS
t
DHS
CLK
FIGURE 15. CLOCK AND RESET TIMING
FIGURE 16. SERIAL INTERFACE RELATIVE TIMING
17

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