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ISL5239KI Datasheet

  • ISL5239KI

  • Pre-Distortion Linearizer

  • 31頁(yè)

  • INTERSIL   INTERSIL

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ISL5239
pre-distorter. The pre-distorter block diagram is shown in
Figure 4.
FROM
IFIP
I
Q
I
Q
PRE-D OR BYPASS
INPUT OR TEST
IF Converter (IFC)
The output of the pre-distorter is a complex baseband signal
sampled at the system CLK rate. To provide greater system
flexibility, the IF Converter function can change this in one of
three different ways, providing frequency shifts, sample rate
changes and complex to real conversions.
I
Q
CM TEST
LUT
ADDRESS
CALCULATION
Real 1X
The real 1x operating mode shifts the signal up by Fs/4 and
performs a complex to real conversion without changing the
base sample rate. This mode has 1/2 the bandwidth of the
original input signal, with the I output channel active and the
Q output channel set to 0. The operation of the IF converter
in this mode is shown in Figure 5.
BYPASS
TEST
FUNC. SEL.
OFFSET
SCALE
PD MAG.
LUT DATA I
LUT DATA Q
LUT DELTA DATA I
LUT DELTA DATA Q
ACTIVE LUT
LUT ADDR
LUT ADDR AUTO INCR.
COEF. B SELECT
SERIAL INPUT EN.
PWR INTGR PER.
PWR LOW
PWR HIGH
BYPASS
POWER
ADDR
LUT
DATA
MEMORY EFFECT
COMPENSATION
I
Q
FROM
PD
HALF
BAND
FILTER
e
j(pi/2)(n)
I
Re{*}
FIGURE 5. IF CONVERTER IN REAL 1X MODE OPERATION
POWER
INTEGRATOR
COEF. A
COEF. B
SERIAL TO PAR.
SERIN
Real 2X
The real 2x operating mode converts complex to real at 2x
the sample rate and shifts the signal up to Fs/2 (Fs/4 of the
output rate). This mode has the same bandwidth as the
original signal with the I channel carrying the first of twwo
samples/clock and the Q channel carrying the second
sample. The operation of the IF Converter in this mode is
shown in Figure 6.
BYPASS
I
Q
FROM
PD
2
2
HALF
BAND
FILTER
e
j(pi/2)(n)
Z
-1
2
2
I
Q
SER. OUTPUT EN.
PAR. TO SERIAL
SERCLK
SERSYNC
SEROUT
EXTERNAL
MEMORY
EFFECTS
FPGA
FIGURE 4. PRE-DISTORTER BLOCK DIAGRAM
Serial Interface
The serial interface for the external memory effects
calculation consists of outputs SERCLK, SERSYNC, and
SEROUT and input SERIN. The serial output sends the 32-
bit unsigned average power off-chip for further processing.
The data is transmitted via the SEROUT pin MSB first, with
the first bit marked by a high pulse on the SERSYNC pin.
The SERCLK rate is scaled such that 32 bits are transmitted
in one period of the power integrator as controlled by register
0x18 bits 5:4. SEROUT is enabled by register 0x18 bit 12.
The SERIN receives the thermal compensation parameters
from external processing using the same SERCLK and
SERSYNC used by the SEROUT. The chip expects to
receive 32 bits of data sequentially on the SERIN pin: the
MSB of A, followed by the rest of A, then the MSB of B,
followed by the rest of B. The SERIN is enabled by register
0x18 bit 8. When SERIN is disabled, registers 0x19 and
0x1a supply the A and B parameters for the thermal
compensation calculations. See Figure 16 for a detailed
timing diagram of the serial interface.
Re{*}
FIGURE 6. IF CONVERTER IN REAL 2X MODE OPERATION
8

ISL5239KI 產(chǎn)品屬性

  • Intersil

  • 1.8 V

  • 300 mA

  • BGA

  • Tray

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