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Functional Block Diagram

ISL5239 Pre-Distortion Linearizer

IIN<17:0>

QIN<17:0>

CLKOUT

OFFSET

BINARY

MUX

BYPASS

BYPASS

BYPASS

PRE-D OR BYPASS

PD I,Q

INPUT OR TEST

BYPASS

IF

CONV.

BYPASS

CORRECTION

FILTER

REAL 1X

REAL 2X

COMPLEX

BYPASS

GAIN /

PHASE

OFFSET

ADJUST.

OUTPUT

DATA

FORMATTER

8-18 BIT-WIDTH

IOUT<17:0>

QOUT<17:0>

DE-MUX

ISTRB

INPUT TYPE

(PAR/SERIAL)

HALF

HALF

HALF

BAND

BAND

BAND I /

FILTER

FILTER

FILTER

Q

/ /

/ /

/

1

2

3

20

18

20

IFIP I,Q

I

CM TEST

Q

TEST

FUNC. SEL.

OFFSET

SCALE

PD MAG.

LUT DATA I

LUT DATA Q

LUT DELTA DATA I

LUT DELTA DATA Q

ACTIVE LUT

LUT ADDR

LUT ADDR AUTO INCR.

PWR INTGR PER.

PWR LOW

PWR HIGH

LUT

ADDRESS

CALCULATION

ADDR

BYPASS

MODE

HM, KM, LM, GM, DC OFFSETS

OUTPUT WORD WIDTH SEL.

OUTPUT VALUE TYPE

COEF. DATA

REAL PIPELINE SEL.

COEF. ADDR.

SERIAL INPUT EN.

COEF. B SELECT

JTAG

POWER

3

DATA

LUT

CHANNEL 3

MEMORY EFFECT

COMPENSATION

TMS

TDI

TCK

TRST

TDO

ISL5239

TRIGIN

PD MAG.

MAX

MIN

uP

TRIG SEL

IFIP I,Q

PD I,Q

PD MAG.

INPUT

SEL

DATA

TRIGOUT

COEF. A

COEF. B

SERIAL TO PAR.

POWER

INTEGRATOR

THRESHOLD

COMPARE

TRIG

SER. OUTPUT EN.

FB DELAY COUNT

PAR. TO SERIAL

INPUT DELAY

COUNT

uP

INPUT

STATE

FB

STATE

SERIN

SERCLK

SERSYNC

SEROUT

EXTERNAL

MEMORY

EFFECTS

FPGA

FBCLK

FB<19:0>

uP FORMAT

ADDR

ADDR

DATA

INPUT

CAPTURE

MEMORY 2K

CM TEST I,Q

MEMORY SELECT

FEEDBACK

CAPTURE

MEMORY 1K

CLK

A<5:0>

P<15:0>

CS

WR

RD

BUSY

RESET

uP INTERFACE

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