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ISL5239KI Datasheet

  • ISL5239KI

  • Pre-Distortion Linearizer

  • 31頁(yè)

  • INTERSIL   INTERSIL

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ISL5239
AC Electrical Specifications
V
CCC
= 1.8鹵 5%, V
CCIO
= 3.3 鹵 5%, T
A
= -40
o
C to 85
o
C (Note 6)
SYMBOL
f
CLK
t
CLK
t
CH
t
CL
t
RS
t
RH
t
RPW
t
PSW
t
PHW
t
ASW
t
AHW
t
CSW
t
CHW
t
BDW
t
WSC
t
WHC
t
WPWH
t
WPWL
t
RSR
t
RHR
t
CSR
t
CHR
t
ASR
t
ASC
t
RE
t
RD
t
DR1
t
DS
t
DH
t
CC01
t
CC0N
t
PDC1
t
CFBD
t
FS
t
FH
t
SD1
t
SD2
t
SC1
t
SCN
t
DSS
2 (Note 7)
-0.1
2
1
2 (Note 7)
2 (Note 7)
2 (Note 7)
2 (Note 7)
1
7
8
9
8
MIN
-
8.0
3
3
2
2
2
1
4
0
4
0
3
-
3
0
3
3
1
2
1
2
-2
3
-
-
-
2
2
MAX
125
-
-
-
-
-
-
-
-
-
-
-
-
8
-
-
-
-
-
-
-
-
-
-
8
6
7
-
-
7
8
8
t
CLK
- 2
UNITS
MHz
ns
ns
ns
ns
ns
CLK Cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK Cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETER
CLK Frequency
CLK Period
CLK High, FBCLK High
CLK Low, FBCLK Low
Setup Time RESET High to CLK (Note 8)
Hold RESET High from CLK
RESET Low Pulse Width (Note 7)
Setup Time P<15:0> to WR
Hold Time P<15:0> from WR
Setup Time A<5:0> to WR
Hold Time A<5:0> from WR
Setup Time CS to WR
Hold Time CS from WR
Delay Time from WR to BUSY
Setup Time WR to CLK (Note 9)
Hold Time WR from CLK
WR Pulse Width High
WR Pulse Width Low
Setup Time from RD to CLK
Hold Time RD from CLK
Setup Time from CS to CLK
Hold Time CS from CLK
Setup Time from A<5:0> to CS and RD (Note 7)
Setup Time from A<5:0> to CLK
Delay Time from CS and RD to P<15:0> Enable (Note 7)
Delay Time from CS and RD to P<15:0> Disable (Note 7)
Delay Time from CLK to P<15:0> valid
Setup Time IIN<17:0>, QIN<17:0>, or ISTRB to CLK
Hold Time IIN<17:0>, QIN<17:0>, or ISTRB from CLK
Delay Time from CLK to CLKOUT in x1 Mode
Delay Time from CLK to CLKOUT in x2, x4, x8 Mode
Delay Time from CLK to IOUT<17:0>, QOUT<17:0> valid
Time Skew from CLK to FBCLK (Note 7)
Setup Time from FB<19:0> to FBCLK
Hold Time FB<19:0> from FBCLK
Delay Time from CLK to SERSYNC
Delay Time from CLK to SEROUT
Delay Time from CLK to SERCLK in Period_32 Mode
Delay Time from CLK to SERCLK in Period_64 or Period_128 Modes
Setup Time from SERIN to CLK (Note 7)
16

ISL5239KI 產(chǎn)品屬性

  • Intersil

  • 1.8 V

  • 300 mA

  • BGA

  • Tray

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