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ISL5217KIZ Datasheet

  • ISL5217KIZ

  • Quad Programmable Up Converter

  • 799.82KB

  • 43頁

  • INTERSIL   INTERSIL

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ISL5217
AC Electrical Specifications
V
CCC
= 2.5 鹵 5%, V
CCIO
= 3.3 鹵 5%, T
A
= -40
o
C to 85
o
C (Note 6)
(Continued)
SYMBOL
t
IQIDC
t
IQODC
t
IQVC2X
t
IQVC2X
t
SVC1X
tSVC
t
IDC
t
FDC
t
SDC
t
PDC
t
PDAC
t
PDAC1
t
RF
MIN
2
2
2
2
2
2
2
-
-
-
-
-
-
MAX
7
7
8
8
7
7
6
7
9
16
20
20
3
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETER
IIN<19:0> or QIN<19:0> Delay Time from CLK
IOUT<19:0> or QOUT<19:0> Delay Time from CLK
IIN<19:0> or QIN<19:0> Valid Time from CLK, 2X Rate
IOUT<19:0> or QOUT<19:0> Valid Time from CLK, 2X Rate
SCLKX Valid Time from CLK, SCLX = CLK
SCLKX Valid Time from CLK, SCLX = Divided CLK
ISTRB Delay Time from CLK
FSRX Delay Time from CLK
SYNCO Delay Time from CLK
P<15:0> Delay Time from CLK
P<15:0> Delay Time from A<6:0> or CS
P<15:0> Delay Time from A<6:0> or CS (RDMODE=1)
Output Rise/Fall Time (Note 7)
NOTES:
6. AC tests performed with C
L
= 70pF. Input reference level for CLK is 1.5V, all other inputs 1.5V.
Test V
IH
= 3.0V, V
IHC
= 3.0V, V
IL
= 0V, V
OL
= 1.5V, V
OH
= 1.5V.
7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
AC Test Load Circuit
DUT
S
1
C
L
鈥?/div>
鹵
SWITCH S
1
OPEN FOR I
CCSB
AND I
CCOP
I
OH
1.5V
I
OL
鈥?/div>
TEST HEAD CAPACITANCE
EQUIVALENT CIRCUIT
Waveforms
t
CLK
t
CH
t
CL
t
CLK
= 1 / F
CLK
CLK
t
SVC
SCLKX
t
FDC
CLK
t
RHC
t
RPW
RESET
SDX
t
RSC
FSRX
t
SSS
t
SHS
FIGURE 19. CLOCK AND RESET TIMING
FIGURE 20. SERIAL INTERFACE RELATIVE TIMING
23
FN6004.3
July 8, 2005

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