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ISL5216

TABLE 50. TABLE OF INDIRECT READ ADDRESS (IRA) REGISTERS

IRA

*003h

*004h

*005h

*007h

*008h

*00Ah

*00Bh

*00Ch

*00Dh

*00Eh

*00Fh

*010h

*011h

*012h

*013h

*014h

*015h

*016h

*017h

*018h

*01Ch

*100h - *17Fh

*180h - *1FCh

*400h - *43Fh

*440h - *47Fh

*480h - *4FFh

*500h - *5FFh

F800h

F801h

F802h

F803h

F804h

F805h

F806h

F807h

F80Bh

5:0

19:0

31:0

31:0

31:8

31:0

13:0

31:0

8:0

15:0

15:0

31:0

31:0

15:0

10:0

31:0

31:0

23:0

31:0

23:0

15:0

31:0

30:0

31:8

31:8

31:8

31:8

31:0

23:0

31:0

31:0

20:0

21:0

31:0

15:0

31:0

BITS

CIC Destination FIR and Output Enable/Disable

Carrier NCO / CIC Control

Active Carrier NCO Center Frequency.

Timing NCO Frequency (upper 32 bits)

Timing NCO Frequency (lower 24 bits)

Filter Compute Engine / Resampler Control

Filter Start Offset

Wait Threshold / Decrement Value

Reset Write Pointer Offset

AGC gain load register (reads gain initially loaded into AGC gain register)

AGC gain read (must first write to AGC gain read strobe register IWA = *00Fh before reading)

AGC Loop Attack / Decay Gain Values

AGC Gain Limits

AGC Threshold

AGC / Discriminator Control

Serial Data Output Control

Serial Data Output 1 Content / Format (Register 1)

Serial Data Output 1 Content / Format (Register 2)

Serial Data Output 2 Content / Format (Register 1)

Serial Data Output 2 Content / Format (Register 2)

Carrier Phase Offset

Instruction RAMs.

Instruction RAMs (pointer RAM).

Coefficient ROM -HBF, const.

Coefficient RAM -1.

Coefficient RAM -2.

Coefficient ROM -Resampler.

Test Control

Bus Routing Control

Reset / SYNC / Interrupt Source Selection

Serial Clock Control

Input Level Detector Source Select

Input Level Detector Configuration

Input Level Detector result (valid when bit 1 of status word is set)

碌P

/ Test Input Bus

BIST

碌P

FIFO Read Order Control

FUNCTION

F820h - F83Fh 4:0

48

July 8, 2005

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