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ISL5216

TABLE 34. FILTER COMPUTE ENGINE INSTRUCTION RAMS (IWA = *100h THRU *17Fh)

P(31:0)

31:0

FUNCTION

These locations in RAM are used to store the Filter Compute Engine instruction words. There are 128 bits per instruction word with

each word consisting of condition code selects, FIR parameters and data routing controls. The filter compute engine is controlled by

a simple sequencer supporting up to 32 steps where each step is defined by a 128-bit instruction word. This instruction word is

assigned to RAM memory in four 32-bit data writes through the Microprocessor Interface starting with the low 32 bits. Hence, 128

32-bit memory locations are required per channel to support the 32 steps of the Filter Sequencer. See the

Filter Compute Engine

and

Filter Sequencer

sections of the data sheet for more details.

TABLE 35. FILTER COMPUTE ENGINE INSTRUCTION POINTER RAMS (IWA = *180h THRU *1FCh)

P(15:0)

(no programming required)

TABLE 36. FILTER COMPUTE ENGINE COEFFICIENT RAM (IWA = *440h THRU *4FFh)

P(31:0)

31:8

FUNCTION

These locations in RAM are used to store the 22-bit filter coefficients used by the Filter Compute Engine of each channel in

implementing a FIR filter. The 22-bit FIR filter coefficients are loaded in the upper 22 bits of each 32-bit RAM location. The two LSBs

of the second byte (bits 9:8 of the total 32 bits, 31:0) are the shift bits. These are set to zero if not used. The least significant byte

(bits 7:0 of the total 32 bits, 31:0) are ignored. The coefficient RAM address space allows for storage of 192 filter coefficients storage

locations. See the

Filter Compute Engine

and

Filter Sequencer

sections of the data sheet for more details.

FUNCTION

Tables of Global Write Address (GWA) Registers

NOTE: These Global Write Addresses control global functions on the ISL5216, so they are not repeated for each channel. The top five address bits

select this set of registers (F8XXh).

TABLE 37. TEST CONTROL REGISTER (GWA = F800h)

P(31:0)

31:21

FUNCTION

These bits can be routed to the output pins by setting bit 16 below. The bit to pin mapping is:

31 = Intrpt

28 = SYNCA

24 = SD1A

30 = SYNCO

27 = SYNCB

23 = SD1B

29 = SERCLK (unless x1 CLK is selected)

26 = SYNCC

22 = SD1C

25 = SYNCD

21 = SD1D

This is provided for testing board level interconnects. To control the SERCLK output, a divided down clock must be selected in the

serial clock control register (GWA = F803h).

20:17

16

15

14:10

9

8

7:4

Unused - set to zero.

This bit, when high, routes bits 31:17 to the output pins in place of the normal outputs.

Data RAM test access enable: set to 1 to access data RAM for testing, set to 0 for normal operation

Unused - set to zero.

Set to 0.

Set to 0.

These bits, when set, route the MSB of the SIN output of the channel鈥檚 carrier NCO to the number two serial output pin in place of

the normal output. 7=CH0 6=CH1 5=CH2 4=CH3.

Offset I PN by XORing bit 10 of the PN generator with the output PN.

Enable (2

23

- 1) PN generator. The PN signal that can be added to the mixer output of each channel is produced from a (2

23

- 1)

sequence, a (2

15

- 1) sequence or both. Two separate generators are provided. The outputs of both are XORed together to extend

the repeat period. Either or both generators can be disabled. The XORed output can further be XORed with a delayed version of the

(2

23

- 1) sequence on the I channel to decorrelate it from the Q channel. Otherwise, the same sequence will be used on both I and Q.

Enable (2

15

- 1) PN generator.

Test mode. When asserted, this bit puts the chip into internal (self) test mode.

Set to 1 to enter a Self Test Mode.

3

2

1

0

43

July 8, 2005

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