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ISL5314IN Datasheet

  • ISL5314IN

  • Direct Digital Synthesizer

  • 16頁

  • INTERSIL   INTERSIL

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ISL5314
Electrical Specifications
PARAMETER
Address Hold Time, t
AH
UPDATE Pulse Width, t
UW
UPDATE Setup Time, t
US
UPDATE Hold Time, t
UH
UPDATE Latency, t
UL
UPDATE Latency, t
UL
Maximum PH Rate
Phase Pulse Width, t
PW
Phase Setup Time, t
PS
Phase Hold Time, t
PH
Phase Latency, t
PL
Maximum ENOFR Rate
ENOFR Pulse Width, t
EW
ENOFR Setup Time, t
ES
ENOFR Hold Time, t
EH
ENOFR Latency, t
EL
Write Enable Pulse Width, t
WR
Write Enable Setup Time, t
WS
Write Enable Hold Time, t
WH
RESET Pulse Width, t
RW
RESET Setup Time, t
RS
RESET Latency to Output, t
RL
RESET Latency to Write, t
RE
Maximum SCLK Rate
SCLK Pulse Width, t
SCW
SDATA Pulse Width, t
SDW
SDATA Setup Time, t
SDS
SDATA Hold Time, t
SDH
SSYNC Pulse Width, t
SSW
SSYNC Setup Time, t
SSS
SSYNC Hold Time, t
SSH
AV
DD
= DV
DD
= +5V (unless otherwise noted), V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= -40
o
C to 85
o
C for
all Min and Max Values. T
A
= 25
o
C for All Typical Values
(Continued)
TEST CONDITIONS
Between ADDR and WR (Note 3)
(Note 3)
Between UPDATE and CLK (Note 3)
Between UPDATE and CLK (Note 3)
After UPDATE, before analog output change, if asserted after
writing to the control registers
After UPDATE, before analog output change, if asserted before
writing to the control registers
Rate of PH1 and PH0 pins (Note 3)
PH(1:0) (Note 3)
Between PH(1:0) change and CLK (Note 3)
Between PH(1:0) change and CLK (Note 3)
Between PH(1:0) change and analog output change
Rate of ENOFR (Note 3)
ENOFR (Note 3)
Between ENOFR and CLK (Note 3)
Between ENOFR and CLK (Note 3)
After ENOFR, before analog output change
WE (Note 3)
Between WE and WR (Note 3)
Between WE and WR (Note 3)
RESET (Note 3)
Between RESET and CLK
After RESET, before analog output reflects reset values
After RESET, before the control registers can be written to
See Figure 6 Timing Diagrams (Note 3)
See Figure 6 Timing Diagrams (Note 3)
See Figure 6 Timing Diagrams (Note 3)
Between SDATA and SCLK. See Figure 6 Timing Diagrams. (Note
3)
Between SDATA and SCLK. See Figure 6 Timing Diagrams. (Note
3)
See Figure 6 Timing Diagrams (Note 3)
Between SSYNC and SCLK. See Figure 6 Timing Diagrams.
(Note 3)
Between SSYNC and SCLK. See Figure 6 Timing Diagrams.
(Note 3)
MIN
0
5
1
3
-
-
f
CLK
/2
5
1
3
-
f
CLK
/2
5
1
3
-
5
2
4
5
1
-
-
50
5
5
6
1
5
6
1
TYP
-
-
-
-
14
11
-
-
-
-
12
-
-
-
-
14
-
-
-
-
-
11
1
-
-
-
-
-
-
-
-
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UNITS
ns
ns
ns
ns
Clock
Cycles
Clock
Cycles
Hz
ns
ns
ns
Clock
Cycles
Hz
ns
ns
ns
Clock
Cycles
ns
ns
ns
ns
ns
Clock
Cycles
Clock
Cycles
MSPS
ns
ns
ns
ns
ns
ns
ns
9

ISL5314IN PDF文件相關(guān)型號

ISL54400IRUZ,ISL54400IRUZ-T,ISL54400IRZ,ISL54401IRUZ,ISL54401IRZ,ISL54401IRZ-T,ISL54402,ISL54402IRUZ,ISL54402IRUZ-T,ISL55001IBZ-T13,ISL55001IBZ-T7

ISL5314IN 產(chǎn)品屬性

  • 250

  • 集成電路 (IC)

  • 接口 - 直接數(shù)字合成 (DDS)

  • -

  • 14 b

  • 125MHz

  • 48 b

  • 3 V ~ 5.5 V，4.5 V ~ 5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 48-LQFP

  • 48-TQFP（7x7）

  • 托盤

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