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ISL5314IN Datasheet

  • ISL5314IN

  • Direct Digital Synthesizer

  • 16頁(yè)

  • INTERSIL   INTERSIL

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ISL5314
Pin Descriptions
PIN NO.
44-48, 1-3
42
40
35-38
6
8
30
27
32
9
33, 34
PIN NAME
C(7:0)
WR
WE
A(3:0)
CLK
RESET
SCLK
SDATA
SSYNC
UPDATE
PH(1:0)
TYPE
Input
Input
Input
Input
Clock
Input
Input
Input
Input
Input
Input
PIN DESCRIPTION
8-bit processor input data bus. C7 is the MSB. Data is written to the control register selected on
A(3:0) on the rising edge of WR when WE is active.
Write clock for the processor interface. Parallel data is clocked into the chip on the rising edge of
WR.
Write enable. Active low. WE must be active when writing data to the chip.
Processor interface address bus. These pins select the destination register for data on the C(7:0)
bus. A3 is the MSB.
NCO and DAC clock. The phase accumulator and DAC output update on the rising edge of this
clock. CLK can be asynchronous to the WR clock.
Reset. Active low. Resets control registers to their default states (see register description table)
and zeroes the feedback in the phase accumulator. UPDATE must be low for Reset to occur.
Serial clock. Polarity is programmable. See control word 12. May be asynchronous to CLK. If not
used, connect to DGND.
Serial data. See control word 12. If not used, connect to DGND.
Serial sync. See control word 12. If not used, connect to DGND.
Active low. Updates the active control registers only. It has no effect on the ENOFR or PH(1:0)
pins. This pin is provided for updating an entire frequency word at once rather than byte by byte.
Phase offset bits. The phase of the output is shifted. If not used, these pins should be grounded.
00 鈥?0 degrees reference
01 鈥?90 degrees shift
10 鈥?180 degrees shift
11 鈥?270 degrees shift
Enable offset frequency. Active high. When high, the offset frequency bus is enabled to the phase
accumulator. When low, the offset frequency bus is zeroed. This pin does not affect the contents
of the offset frequency registers. If not used, the pin should be grounded.
Comparator output.
Connect to analog ground to enable the DAC鈥檚 internal 1.2V reference or connect to AV
DD
to
disable the internal reference.
Reference voltage input for the DAC if internal reference is disabled. Recommend the use of a
0.1碌F cap to ground from the REFIO pin when a DC reference voltage is used.
Full scale current adjust for the DAC. Use a resistor to ground (R
SET
) to adjust the full scale
output current. Full Scale Output Current = 32 x V
FSADJ
/R
SET
, where V
FSADJ
equals the
reference voltage.
Noise reduction for the DAC. Connect a 0.1碌F cap to AV
DD
plane.
Noise reduction for the DAC. Connect a 0.1碌F cap to AGND plane.
Output
Output
Power
GND
Power
GND
Input
NC
DAC current output.
DAC complementary current output.
Analog supply voltage.
Analog ground.
Digital supply voltage.
Digital ground.
Comparator inputs. To power down the comparator, connect both of these pins to the analog
power supply. This will conserve ~4mA of current.
No connect.
4
ENOFR
Input
10
11
12
13
COMPOUT
REFLO
REFIO
FSADJ
Output
Input
Input
14
19
18
17
20
15, 16, 21, 24
7, 26, 31, 43
5, 25, 28, 29, 41
22, 23
39
COMP1
COMP2
IOUTA
IOUTB
AV
DD
AGND
DV
DD
DGND
IN+, IN-
NC
14

ISL5314IN PDF文件相關(guān)型號(hào)

ISL54400IRUZ,ISL54400IRUZ-T,ISL54400IRZ,ISL54401IRUZ,ISL54401IRZ,ISL54401IRZ-T,ISL54402,ISL54402IRUZ,ISL54402IRUZ-T,ISL55001IBZ-T13,ISL55001IBZ-T7

ISL5314IN 產(chǎn)品屬性

  • 250

  • 集成電路 (IC)

  • 接口 - 直接數(shù)字合成 (DDS)

  • -

  • 14 b

  • 125MHz

  • 48 b

  • 3 V ~ 5.5 V，4.5 V ~ 5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 48-LQFP

  • 48-TQFP（7x7）

  • 托盤(pán)

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