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ISL5585

Pin Description

PLCC

QFN

SYMBOL

DESCRIPTION

1

2

3

4

5

6

7

8

9

10

11

29

30

31

32

1

2

3

4

5

6

7

TIP

BGND

VBL

VBH

SW+

SW-

SWC

F2

F1

F0

E0

TIP power amplifier output.

Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this

ground. Internally separate from AGND. This ground must be connected to the same potential as AGND.

Low battery supply connection.

High battery supply connection for the most negative battery.

Uncommitted switch positive terminal.

Uncommitted switch negative terminal.

Switch control input. This TTL compatible input controls the uncommitted switch, with a logic 鈥?鈥?enabling

the switch and logic 鈥?鈥?disabling the switch.

Mode Control Input - MSB. F2-F0 for the TTL compatible parallel control interface for controlling the

various modes of operation of the device.

Mode control input.

Mode control input.

Detector Output Selection Input. This TTL input controls the multiplexing of the SHD (E0 = 1) and GKD

(E0 = 0) comparator outputs to the DET output based upon the state at the F2-F0 pins (see the Device

Operating Modes table shown on page 2).

Detector Output - This TTL output provides on-hook/off-hook status of the loop based upon the selected

operating mode. The detected output will either be switch hook, ground key or ring trip (see the Device

Operating Modes table shown on page 2). DET will be latched low following a ring trip. Unlatching the

DET pin is accomplished by changing logic state.

Thermal Shutdown Alarm. This pin signals the internal die temperature has exceeded safe operating

temperature (approximately 175

o

C) and the device has been powered down automatically.

Analog ground reference. This pin should be externally connected to BGND.

Selects between high and low battery, with a logic 鈥?鈥?selecting the high battery and logic 鈥?鈥?the low

battery.

Programming pin for the transient current limit feature, set by an external resistor to ground.

External capacitor on this pin sets the polarity reversal time.

Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode.

Auxiliary input - Float if not used.

Transmit Output Voltage - Output of impedance matching amplifier, AC couples through a resistor to

CODEC.

Feedback voltage for impedance matching. This voltage is scaled to accomplish impedance matching.

The CFB capacitor connects between this pin and the -IN pin. The CFB cap needs to be non-polarized

for proper device operation in the Reverse Active mode. Ceramic surface mount capacitors (1206 body

style) are available from Panasonic with a 6.3V voltage rating. These can be used for CFB since it is

internally limited to approximately 鹵3V.

Analog Receive Voltage - 4-wire analog audio input voltage. connects to CODEC via receive gain setting

resistor R

IN

(see Figure 18). Resistor R

IN

needs to be as close to the -IN pin as possible to minimize

parasitic capacitance.

Positive voltage power supply,+3.3V

DC Biasing Filter Capacitor - Connects between this pin and V

CC

.The CDC capacitor may be either

polarized or non polarized with a 6.3V voltage rating.

Ring trip filter network.

Loop Current Limit programming resistor.

Switch hook detection threshold programming resistor.

Substrate Common Connection - Connect this pin to VBH Supply. This pin is used to connect the

substrate of the die and the thermal heatsink plane of the QFN package.

RING power amplifier output.

12

9

DET

13

14

15

16

17

18

19

20

21

10

11

12

13

14

15

17

18

19

ALM

AGND

BSEL

TL

POL

VRS

AUX

VTX

VFB

22

20

-IN

23

24

25

26

27

---

28

21

22

23

24

25

26

27

VCC

CDC

RT

ILIM

SH

SCC

RING

3

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