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ISL5761IAZ Datasheet

  • ISL5761IAZ

  • 10-bit, +3.3V, 130/210+MSPS, High Speed D/A Converter

  • 13頁

  • INTERSIL   INTERSIL

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ISL5761
Electrical Specifications
PARAMETER
Spurious Free Dynamic Range,
SFDR to Nyquist (f
CLK
/2)
AV
DD
= DV
DD
= +3.3V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values
(Continued)
T
A
= -40
o
C TO 85
o
C
TEST CONDITIONS
f
CLK
= 210MSPS, f
OUT
= 80.8MHz (Notes 4, 7)
f
CLK
= 210MSPS, f
OUT
= 40.4MHz (Notes 4, 7, 9)
f
CLK
= 200MSPS, f
OUT
= 20.2MHz, T = 25
o
C (Notes 4, 7)
f
CLK
= 200MSPS, f
OUT
= 20.2MHz, T = -40
o
C to 85
o
C (Notes 4, 7)
f
CLK
= 130MSPS, f
OUT
= 50.5MHz (Notes 4, 7)
f
CLK
= 130MSPS, f
OUT
= 40.4MHz (Notes 4, 7)
f
CLK
= 130MSPS, f
OUT
= 20.2MHz (Notes 4, 7)
f
CLK
= 130MSPS, f
OUT
= 10.1MHz (Notes 4, 7)
f
CLK
= 130MSPS, f
OUT
= 5.05MHz, T = 25
o
C (Notes 4, 7)
f
CLK
= 130MSPS, f
OUT
= 5.05MHz, T = -40
o
C to 85
o
C (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 40.4MHz (Notes 4, 7)
f
CLK
= 80MSPS, f
OUT
= 30.3MHz (Notes 4, 7)
f
CLK
= 80MSPS, f
OUT
= 20.2MHz (Notes 4, 7)
f
CLK
= 80MSPS, f
OUT
= 10.1MHz (Notes 4, 7, 9)
f
CLK
= 80MSPS, f
OUT
= 5.05MHz (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 20.2MHz (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 10.1MHz (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 5.05MHz (Notes 4, 7)
Spurious Free Dynamic Range,
SFDR in a Window with Eight Tones
f
CLK
= 210MSPS, f
OUT
= 28.3MHz to 45.2MHz, 2.1MHz Spacing,
50MHz Span (Notes 4, 7, 9)
f
CLK
= 130MSPS, f
OUT
=17.5MHz to 27.9MHz, 1.3MHz Spacing,
35MHz Span (Notes 4, 7)
f
CLK
= 80MSPS, f
OUT
= 10.8MHz to 17.2MHz, 811kHz Spacing,
15MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 6.7MHz to 10.8MHz, 490kHz Spacing,
10MHz Span (Notes 4, 7)
Spurious Free Dynamic Range,
f
CLK
= 78MSPS, f
OUT
= 11MHz, in a 20MHz Window, RBW=30kHz
SFDR in a Window with EDGE or GSM (Notes 4, 7, 9)
Adjacent Channel Power Ratio,
ACPR with UMTS
VOLTAGE REFERENCE
Internal Reference Voltage, V
FSADJ
Internal Reference Voltage Drift
Internal Reference Output Current
Sink/Source Capability
Reference Input Impedance
Reference Input Multiplying Bandwidth (Note 7)
DIGITAL INPUTS
D9-D0, CLK
(Note 3)
(Note 3)
2.3
-
-25
3.3
0
-
-
1.0
+25
V
V
碌A(chǔ)
Reference is not intended to be externally loaded (REFIO pin)
Pin 18 Voltage with Internal Reference
1.2
-
-
-
-
1.23
鹵40
0
1
1.0
1.3
-
-
-
-
V
ppm/
o
C
碌A(chǔ)
M鈩?/div>
MHz
f
CLK
= 76.8MSPS, f
OUT
= 19.2MHz, RBW=30kHz (Notes 4, 7, 9)
MIN
-
-
58
56
-
-
-
-
68
66
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP
50
58
60
-
55
60
68
70
75
-
58
61
67
69
74
66
72
75
63
66
73
75
83
65
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UNITS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
Input Logic High Voltage with
3.3V Supply, V
IH
Input Logic Low Voltage with
3.3V Supply, V
IL
Sleep Input Current, I
IH
5

ISL5761IAZ 產(chǎn)品屬性

  • Solutions for Industrial Control Applications

  • 50

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器

  • -

  • -

  • 10

  • 并聯(lián)

  • 1

  • 單電源

  • 120mW

  • -40°C ~ 85°C

  • 表面貼裝

  • 28-TSSOP（0.173"，4.40mm 寬）

  • 28-TSSOP

  • 管件

  • 2 電流，單極

  • 150M

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