ISL5761
Absolute Maximum Ratings
Digital Supply Voltage DV
DD
to DCOM . . . . . . . . . . . . . . . . . . +3.6V
Analog Supply Voltage AV
DD
to ACOM . . . . . . . . . . . . . . . . . . +3.6V
Grounds, ACOM TO DCOM. . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . DV
DD
+ 0.3V
Reference Input Voltage Range . . . . . . . . . . . . . . . . . . AV
DD
+ 0.3V
Analog Output Current (I
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Information
Thermal Resistance (Typical, Note 1)
胃
JA
(
o
C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
CAUTION: Stresses above those listed in 鈥淎bsolute Maximum Ratings鈥?may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
胃
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
Offset Error, I
OS
Offset Drift Coefficient
Full Scale Gain Error, FSE
AV
DD
= DV
DD
= +3.3V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values
T
A
= -40
o
C TO 85
o
C
TEST CONDITIONS
MIN
TYP
MAX
UNITS
10
鈥淏est Fit鈥?Straight Line (Note 7)
(Note 7)
IOUTA (Note 7)
(Note 7)
With External Reference (Notes 2, 7)
With Internal Reference (Notes 2, 7)
-0.5
-0.5
-0.006
-
-3
-3
-
-
2
(Note 3)
-1.0
-
鹵0.1
鹵0.1
-
+0.5
+0.5
+0.006
Bits
LSB
LSB
% FSR
ppm
FSR/
o
C
% FSR
% FSR
ppm
FSR/
o
C
ppm
FSR/
o
C
mA
V
0.1
鹵0.5
鹵0.5
鹵50
鹵100
-
-
-
+3
+3
-
-
20
1.25
Full Scale Gain Drift
With External Reference (Note 7)
With Internal Reference (Note 7)
Full Scale Output Current, I
FS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f
CLK
Maximum Clock Rate, f
CLK
Output Rise Time
Output Fall Time
Output Capacitance
Output Noise
IOUTFS = 20mA
IOUTFS = 2mA
AC CHARACTERISTICS
(Using Figure 13 with R
DIFF
= 50鈩?and R
LOAD
= 50鈩? Full Scale Output = -2.5dBm)
Spurious Free Dynamic Range,
SFDR Within a Window
f
CLK
= 210MSPS, f
OUT
= 80.8MHz, 30MHz Span (Notes 4, 7)
f
CLK
= 210MSPS, f
OUT
= 40.4MHz, 30MHz Span (Notes 4, 7)
f
CLK
= 130MSPS, f
OUT
= 20.2MHz, 20MHz Span (Notes 4, 7)
ISL5761/2IA, ISL5761/2IB
ISL5761IA, ISL5761IB
Full Scale Step
Full Scale Step
210
130
-
-
-
-
-
250
150
1.5
1.5
10
50
30
-
-
-
-
-
-
-
MHz
MHz
ns
ns
pF
pA/鈭欻z
pA/鈭欻z
-
-
-
72
75
77
-
-
-
dBc
dBc
dBc
4