ISL5761
Propagation Delay
R
EQ
= 0.5 x (R
LOAD
// R
DIFF
)
AT EACH OUTPUT
V
OUT
= (2 x IOUTA x R
EQ
)V
1:1
R
DIFF
IOUTA
R
LOAD
IOUTB
PIN 21
PIN 22
ISL5761
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
data. The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 15.
Test Service
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form. The form can be found by doing an 鈥榚ntire
site search鈥?at www.intersil.com on the words 鈥楧AC
Testdrive鈥? Or, send a request to the technical support center.
R
LOAD
REPRESENTS THE
LOAD
SEEN BY THE TRANSFORMER
FIGURE 13. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
R
EQ
= 0.5 x (R
LOAD
// R
DIFF
// R
A
), WHERE R
A
=R
B
AT EACH OUTPUT
R
A
IOUTB
PIN 21
R
DIFF
PIN 22
ISL5761
IOUTA
R
B
R
LOAD
V
OUT
= (2 x IOUTA x R
EQ
)V
R
LOAD
REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 14. ALTERNATIVE OUTPUT LOADING
Timing Diagram
t
PW1
t
PW2
CLK
50%
t
SU
t
HLD
D9-D0
W
0
t
SU
t
HLD
W
1
t
SU
t
HLD
W
2
W
3
t
PD
t
PD
OUTPUT=W
0
I
OUT
OUTPUT=W
-1
OUTPUT=W
1
FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
11