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MPC952 Datasheet

  • MPC952

  • Low Voltage PLL Clock Drlver

  • Motorola   Motorola

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MPC952
AC CHARACTERISTICS
(TA = 0擄 to 70擄C, VCC = 3.3V
鹵5%)
Symbol
tr, tf
tpw
tos
Characteristic
Output Rise/Fall Time (Note 4.)
Output Pulse Width (Note 4.)
Output-to-Output Skew
(Note 4.)
PLL VCO Lock Range
Excluding Qa0
All Outputs
All Outputs
Feedback = VCO/4
Feedback = VCO/6
Feedback = VCO/8
Feedback = VCO/12
Qc,Qb (梅2)
Qa,Qb,Qc (梅4)
Qa (梅6)
200
200
200
200
180
120
80
鈥?00
2
2
鹵100
10
0
200
8
10
Min
0.10
tCYCLE/2
鈥?50
tCYCLE/2
鹵500
Typ
Max
1.0
tCYCLE/2
+750
350
450
550
480
480
480
480
Unit
ns
ps
ps
Same Frequencies
Same Frequencies
Different Frequencies
VCO_Sel = 0
VCO_Sel = 0
VCO_Sel = 1
VCO_Sel = 1
(Note 4.)
Condition
0.8 to 2.0V
fVCO
MHz
fmax
Maximum Output Frequency
MHz
tpd
tPLZ, tPHZ
tPZL, tPLH
tjitter
tlock
REFCLK to FBIN Delay
Output Disable Time
Output Enable Time
Cycle鈥搕o鈥揅ycle Jitter (Peak鈥搕o鈥揚(yáng)eak)
Maximum PLL Lock Time
ps
ns
ns
ps
ms
Notes 4., 5.
50鈩?to VCC/2
50鈩?to VCC/2
4. 50鈩?to VCC/2.
5. tpd is specified for 50MHz input ref, the window will shrink/grow proportionally from the minimum limit with shorter/longer input reference periods.
The tpd does not include jitter.
APPLICATIONS INFORMATION
Driving Transmission Lines
The MPC952 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 10鈩?the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
In most high performance clock networks point鈥搕o鈥損oint
distribution of signals is the method of choice. In a
point鈥搕o鈥損oint scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50鈩?resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC952 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 3 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC952 clock
driver is effectively doubled due to its capability to drive
multiple lines.
The waveform plots of Figure 4 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC952 output buffers is
more than sufficient to drive 50鈩?transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output鈥搕o鈥搊utput skew of the MPC952. The output waveform
in Figure 4 shows a step in the waveform, this step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 43鈩?series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
MPC952
OUTPUT
BUFFER
IN
7鈩?/div>
RS = 43鈩?/div>
ZO = 50鈩?/div>
OutA
MPC952
OUTPUT
BUFFER
IN
7鈩?/div>
RS = 43鈩?/div>
ZO = 50鈩?/div>
OutB0
RS = 43鈩?/div>
ZO = 50鈩?/div>
OutB1
Figure 3. Single versus Dual Transmission Lines
MOTOROLA
4
ECLinPS and ECLinPS Lite
DL140 鈥?Rev 3

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