II鈩?/div>
microprocessor chip sets. The device features
10 low skew outputs optimized to drive the clock inputs of standard
unbuffered SO鈥揇IMM SDRAM modules. Standard unbuffered SO鈥揇IMM
SDRAM modules require two clocks per module allowing for the device to
drive up to four modules. The output buffers have been optimized to drive
the load presented by the SDRAM module.
The MPC9120 provides output shut off capabilities via an I2C serial
port for applications which plan to use fewer than four modules and desire
to minimize the power dissipation of the chip. Every output clock can be
individually enabled/disabled through fields in the I2C control registers.
After power up the default state is all outputs enabled. In applications
where this default state is acceptable the I2C ports need not be exercised.
MPC9120
1:10 LVCMOS
FANOUT BUFFER
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Supports Intel Pentium鈩?and Pentium
II
Processor Architectures
10 Skew Controlled 3.3V Compatible SDRAM Clocks
I2C Serial Bus Interface
Extensive Output Enable Control Capability
Space Efficient 28鈥揕ead SSOP Package
Operating Temperature Range of 0擄C to 70擄C
3.3V
鹵
5% Power Supply
SD SUFFIX
28鈥揕EAD PLASTIC SSOP PACKAGE
CASE 940E鈥?2
VDD
SDRAM0
SDRAM1
VSSO
VDD
SDRAM2
SDRAM3
VSS
BUF_IN
1
2
3
4
5
6
7
8
9
28 VDD
27 SDRAM9
26 SDRAM8
25 VSS
24 VDD
23 SDRAM7
22 SDRAM6
21 VSS
20 OE
19 VDD
18 SDRAM5
17 VSS
16 VSSIIC
15 SCLOCK
FUNCTION TABLE
OE
0
1
V1, V2
High鈥揨
1x BUF_IN
VDD 10
SDRAM4 11
VSS 12
VDDIIC 13
SDATA 14
Figure 1. 28鈥揕ead Pinout
(Top View)
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
12/97
漏
Motorola, Inc. 1997
1
REV 0.2
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