鈥?/div>
LVPECL or LVCMOS/LVTTL Clock Input
250ps Maximum Targeted Output鈥搕o鈥揙utput Skew
Drives Up to 54 Independent Clock Lines
Maximum Output Frequency of 250MHz
High Impedance Output Enable
52鈥揕ead TQFP Packaging
3.3V VCC Supply Voltage
FA SUFFIX
With a low output impedance, in both the HIGH and LOW logic states,
52鈥揕EAD TQFP PACKAGE
the output buffers of the MPC941 are ideal for driving series terminated
CASE 848D鈥?3
transmission lines. More specifically, each of the 27 MPC941 outputs can
drive two series terminated 50鈩?transmission lines. With this capability,
the MPC941 has an effective fanout of 1:54 in applications where each
line drives a single load. With this level of fanout, the MPC941 provides
enough copies of low skew clocks for most high performance
synchronous systems.
The differential LVPECL inputs of the MPC941 allow the device to interface directly with a LVPECL fanout buffer like the
MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input
provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In
addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH
on the LVCMOS_CLK_Sel pin will select the TTL level clock input.
The MPC941 is fully 3.3V compatible. The 52鈥搇ead TQFP package was chosen to optimize performance, board space and
cost of the device. The 52鈥搇ead TQFP has a 10x10mm body size with a conservative 0.65mm pin spacing.
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
2/97
漏
Motorola, Inc. 1997
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