PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
I2C BUS CONFIGURATION SETTING
Address Assignment
Slave
Receiver/Transmitter
Data Transfer Rate
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
_
Provides both slave write and readback functionality
Standard mode at 100kbits/s
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will
terminate the transfer. The write or read block both begins with the master sending a slave
address and a write condition (0xD2) or a read condition (0xD3).
Following the acknowledge of this address byte, in
Write Mode:
the
Command Byte
and
Byte
Count Byte must be sent by the master
but ignored by the slave, in
Read Mode:
the
Byte
Count Byte
will be
read by the master
then all other
Data Byte. Byte Count Byte
default at
power-up is = (0x09).
Data Protocol
I2C CONTROL REGISTERS
1. BYTE 6: Outputs Register
(1=Enable, 0=Disable)
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin#
48
-
-
-
45, 44
43, 42
39, 38
34, 33
Default
1
0
0
0
1
1
1
1
Description
Reserved
Reserved
Enhanced DDR Drive. 1 = Enhanced 25%
Reserved
DDR11T, DDR11C
DDR10T, DDR10C
DDR9T, DDR9C
DDR8T, DDR8C
2. BYTE 7: Outputs Register
(1=Enable, 0=Disable)
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin#
30,
28,
21,
19,
15,
10,
6,
4,
29
27
22
20
16
11
7
5
Default
1
1
1
1
1
1
1
1
Description
DDR7T,
DDR6T,
DDR5T,
DDR4T,
DDR3T,
DDR2T,
DDR1T,
DDR0T,
DDR7C
DDR6C
DDR5C
DDR4C
DDR3C
DDR2C
DDR1C
DDR0C
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/09/04 Page 3
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