鈥?/div>
Generates 24 output buffers from one input.
Supports up to four DDR DIMMS.
Supports 266MHz DDR SDRAM.
One additional output for feedback.
Less than 5ns delay.
Skew between any outputs is less than 100 ps.
2.5V Supply range.
Enhanced DDR Output Drive selected by I2C.
Available in 48 pin SSOP.
PIN CONFIGURATION
FBOUT
VDD2.5
GND
DDR0T
DDR0C
DDR1T
DDR1C
VDD2.5
GND
DDR2T
DDR2C
VDD2.5
BUF_IN
DDR0T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N/C
VDD2.5
GND
DDR11T
DDR11C
DDR10T
DDR10C
VDD2.5
GND
DDR9T
DDR9C
VDD2.5
PD#
GND
DDR8T
DDR8C
VDD2.5
GND
DDR7T
DDR7C
DDR6T
DDR6C
GND
SCLK
PLL103-02
BLOCK DIAGRAM
SDATA
SCLK
I2C
Control
DDR0C
DDR1T
DDR1C
DDR2T
DDR2C
DDR3T
DDR3C
DDR4T
GND
DDR3T
DDR3C
VDD2.5
GND
DDR4T
DDR4C
DDR5T
DDR5C
VDD2.5
SDATA
Note:
#: Active Low
BUF_IN
DDR4C
DDR5T
DDR5C
DDR6T
DDR6C
DDR7T
DDR7C
DDR8T
DDR8C
DDR9T
DDR9C
DDR10T
DDR10C
DDR11T
DDR11C
DESCRIPTION
The PLL103-02 is designed as a 2.5V buffer to
distribute high-speed clocks in PC applications. The
device has 24 outputs. These outputs can be
configured to support four unbuffered DDR DIMMS.
The PLL103-02 can be used in conjunction with a
clock synthesizer for the VIA Pro 266 chipset.
The PLL103-02 also has an I2C interface, which can
enable or disable each output clock. When powered
up, all output clocks are enabled (have internal pull
ups).
PD#
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/09/04 Page 1
1
2
3
4
5
6
