最新免费av在线观看,亚洲综合一区成人在线,中文字幕精品无码一区二区三区,中文人妻av高清一区二区,中文字幕乱偷无码av先锋

MM74HC221AM Datasheet

  • MM74HC221AM

  • Fairchild Semiconductor [Dual Non-Retriggerable Monostable ...

  • FAIRCHILD

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

MM74HC221A
Theory of Operation
FIGURE 1.
TRIGGER OPERATION
As shown in
Figure 1
and the logic diagram before an input
trigger occurs, the monostable is in the quiescent state with
the Q output LOW, and the timing capacitor C
EXT
com-
pletely charged to V
CC
. When the trigger input A goes from
V
CC
to GND (while inputs B and clear are held to V
CC
) a
valid trigger is recognized, which turns on comparator C1
and N-channel transistor N11. At the same time the output
latch is set. With transistor N1 on, the capacitor C
EXT
rap-
idly discharges toward GND until V
REF1
is reached. At this
point the output of comparator C1 changes state and tran-
sistor N1 turns off. Comparator C1 then turns off while at
the same time comparator C2 turns on. With transistor N1
off, the capacitor C
EXT
begins to charge through the timing
resistor, R
EXT
, toward V
CC
. When the voltage across C
EXT
equals V
REF2
, comparator C2 changes state causing the
output latch to reset (Q goes LOW) while at the same time
disabling comparator C2. This ends the timing cycle with
the monostable in the quiescent state, waiting for the next
trigger.
A valid trigger is also recognized when trigger input B goes
from GND to V
CC
(while input A is at GND and input clear
is at V
CC
2). The MM74HC221 can also be triggered when
clear goes from GND to V
CC
(while A is at Gnd and B is at
V
CC
6).
It should be noted that in the quiescent state C
EXT
is fully
charged to V
CC
causing the current through resistor R
EXT
to be zero. Both comparators are 鈥渙ff鈥?with the total device
current due only to reverse junction leakages. An added
feature of the MM74HC221 is that the output latch is set via
the input trigger without regard to the capacitor voltage.
Thus, propagation delay from trigger to Q is independent of
the value of C
EXT
, R
EXT
, or the duty cycle of the input
waveform.
The MM74HC221 is non-retriggerable and will ignore input
transitions on A and B until it has timed out 3 and 4.
RESET OPERATION
These one shots may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on clear sets the reset latch and causes the capacitor to be
fast charged to V
CC
by turning on transistor Q1 5. When
the voltage on the capacitor reaches V
REF2
, the reset latch
will clear and then be ready to accept another pulse. If the
clear input is held LOW, any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will
not change. Since the Q output is reset when an input low
level is detected on the Clear input, the output pulse T can
be made significantly shorter than the minimum pulse width
specification.
5
www.fairchildsemi.com

MM74HC221AM 產(chǎn)品屬性

  • 48

  • 集成電路 (IC)

  • 邏輯 - 多頻振蕩器

  • 74HC

  • 單穩(wěn)態(tài)

  • 2

  • 是

  • 22ns

  • 5.2mA，5.2mA

  • 2 V ~ 6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 16-SOIC（0.154"，3.90mm 寬）

  • 16-SOIC

  • 管件

MM74HC221AM相關(guān)型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時(shí)間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！