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MC100E451FNG Datasheet

  • MC100E451FNG

  • ON Semiconductor [5V ECL 6−Bit D Register Differe...

  • ONSEMI

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MC10E451, MC100E451
Q
Driver
Device
Q
Z
o
= 50
W
50
W
50
W
D
Z
o
= 50
W
D
Receiver
Device
V
TT
V
TT
= V
CC
鈭?/div>
2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D
鈭?/div>
Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device
MC10E451FN
MC10E451FNG
MC10E451FNR2
MC10E451FNR2G
MC100E451FN
MC100E451FNG
MC100E451FNR2
MC100E451FNR2G
Package
PLCC鈭?8
PLCC鈭?8
(Pb鈭扚ree)
PLCC鈭?8
PLCC鈭?8
(Pb鈭扚ree)
PLCC鈭?8
PLCC鈭?8
(Pb鈭扚ree)
PLCC鈭?8
PLCC鈭?8
(Pb鈭扚ree)
Shipping
鈥?/div>
37 Units / Rail
37 Units / Rail
500 / Tape & Reel
500 / Tape & Reel
37 Units / Rail
37 Units / Rail
500 / Tape & Reel
500 / Tape & Reel
鈥燜or information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
鈭?/div>
ECL Clock Distribution Techniques
鈭?/div>
Designing with PECL (ECL at +5.0 V)
鈭?/div>
ECLinPSt I/O SPiCE Modeling Kit
鈭?/div>
Metastability and the ECLinPS Family
鈭?/div>
Interfacing Between LVDS and ECL
鈭?/div>
The ECL Translator Guide
鈭?/div>
Odd Number Counters Design
鈭?/div>
Marking and Date Codes
鈭?/div>
Termination of ECL Logic Devices
鈭?/div>
Interfacing with ECLinPS
鈭?/div>
AC Characteristics of ECL Devices
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7

MC100E451FNG PDF文件相關(guān)型號(hào)

MC100E451FNR2,MC100E451FNR2G,MC10E451FNG,MC10E451FNR2

MC100E451FNG 產(chǎn)品屬性

  • 37

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 100E

  • 主復(fù)位

  • D 型總線

  • 非反相

  • 1

  • 6

  • 1.1GHz

  • 625ps

  • 正邊沿

  • -

  • 4.2 V ~ 5.7 V

  • 0°C ~ 85°C

  • 表面貼裝

  • 28-LCC（J 形引線）

  • 管件

MC100E451FNG相關(guān)型號(hào)PDF文件下載

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