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MC100ES6226D Datasheet

  • MC100ES6226D

  • Motorola, Inc [2.5/3.3V Differential LVPECL 1:9 Clock Distr...

  • 291.39KB

  • MOTOROLA   MOTOROLA

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Freescale Semiconductor, Inc.
MC100ES6226
Differential
Pulse Generator
Z = 50
ZO = 50鈩?/div>
ZO = 50鈩?/div>
W
RT = 50鈩?/div>
VTT
DUT
MC100ES6226
RT = 50鈩?/div>
VTT
Figure 4. MC100ES6226 AC test reference
Freescale Semiconductor, Inc...
APPLICATIONS INFORMATION
Maintaining Lowest Device Skew
The MC100ES6226 guarantees low output-to-output bank
skew of 35 ps and a part-to-part skew of max. TBD ps. To
ensure low skew clock signals in the application, both outputs
of any differential output pair need to be terminated
identically, even if only one output is used. When fewer than
all nine output pairs are used, identical termination of all
output pairs within the output bank is recommended. If an
entire output bank is not used, it is recommended to leave all
of these outputs open and unterminated. This will reduce the
device power consumption while maintaining minimum
output skew.
Power Supply Bypassing
The MC100ES6226 is a mixed analog/digital product. The
differential architecture of the MC100ES6226 supports low
noise signal operation at high frequencies. In order to
maintain its superior signal quality, all VCC pins should be
bypassed by high-frequency ceramic capacitors connected
to GND. If the spectral frequencies of the internally generated
switching noise on the supply pins cross the series resonant
point of an individual bypass capacitor, its overall impedance
begins to look inductive and thus increases with increasing
frequency. The parallel capacitor combination shown
ensures that a low impedance path to ground exists for
frequencies well above the noise bandwidth.
VCC
33...100 nF
0.1 nF
VCC
MC100ES6226
Figure 5. VCC Power Supply Bypass
TIMING SOLUTIONS
For More Information On This Product,
7
Go to: www.freescale.com
MOTOROLA

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