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LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • 1113.49KB

  • SMSC   SMSC

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
b)
7.
8.
The chip latches the data from the internal data bus for the PData bus and drives the sync that
indicates that no more wait states are required followed by the TAR to complete the write cycle.
Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and
acknowledging the termination of the cycle.
Chip may modify nWRITE and nPDATA in preparation for the next cycle.
7.7
EPP 1.9 Read
The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip inserts
wait states into the LPC I/O read cycle until it has been determined that the read cycle can complete. The
read cycle can complete under the following circumstances:
1.
2.
If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can
complete when nWAIT goes inactive high.
If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before
changing the state of nWRITE or before nDATASTB goes active. The read can complete once
nWAIT is determined inactive.
Read Sequence of Operation
1.
2.
3.
4.
5.
6.
The host initiates an I/O read cycle to the selected EPP register.
If WAIT is not asserted, the chip must wait until WAIT is asserted.
The chip tri-states the PData bus and deasserts nWRITE.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the
nWRITE signal is valid.
Peripheral drives PData bus valid.
Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase
of the cycle.
The chip latches the data from the PData bus for the internal data bus and deasserts nDATASTB
or nADDRSTRB. This marks the beginning of the termination phase.
The chip drives the sync that indicates that no more wait states are required and drives valid data
onto the LAD[3:0] signals, followed by the TAR to complete the read cycle.
7. a)
b)
8.
9.
Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri-
stated.
Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle.
7.8
EPP 1.7 Operation
When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes
are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in
the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the
SPP Control Port and direction is controlled by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is
required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of
the EPP cycle to the end of the cycle. If a time-out occurs, the current EPP cycle is aborted and the time-
out condition is indicated in Status bit 0.
7.8.1
Software Constraints
Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3
are set to zero. Also, bit D5 (PCD) is a logic 鈥?鈥?for an EPP write or a logic 鈥?鈥?for and EPP read.
SMSC LPC47M172
Page 95
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
DATASHEET

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