最新免费av在线观看,亚洲综合一区成人在线,中文字幕精品无码一区二区三区,中文人妻av高清一区二区,中文字幕乱偷无码av先锋

LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • SMSC   SMSC

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 7.1 - Parallel Port Connector
HOST
CONNECTOR
1
2-9
10
11
12
13
14
15
16
17
(1) = Compatible Mode
(3) = High Speed Mode
Note:
For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This
document is available from Microsoft.
SMSC
PIN NUMBER
See Chapter 3
Description of Pin
Functions.
STANDARD
nSTROBE
PD<0:7>
nACK
BUSY
PE
SLCT
nALF
nERROR
nINITP
nSLCTIN
EPP
nWrite
PData<0:7>
Intr
nWait
(User Defined)
(User Defined)
nDatastb
(User Defined)
nRESET
nAddrstrb
ECP
nStrobe
PData<0:7>
nAck
Busy, PeriphAck(3)
PError,
nAckReverse (3)
Select
nAutoFd,
HostAck(3)
nFault (1)
nPeriphRequest (3)
nInit(1)
nReverseRqst(3)
nSelectIn(1,3)
7.4
7.4.1
IBM XT/AT Compatible, Bi-Directional and EPP Modes
Data Port
ADDRESS OFFSET = 00H
The Data Port is located at an offset of 鈥?0H鈥?from the base address. The data register is cleared at
initialization by RESET. During a WRITE operation, the Data Register latches the contents of the internal
data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports.
During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host
CPU.
7.4.2
Status Port
ADDRESS OFFSET = 01H
The Status Port is located at an offset of 鈥?1H鈥?from the base address. The contents of this register are
latched for the duration of a read cycle. The bits of the Status Port are defined as follows:
BIT 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A
logic O means that no time out error has occurred; a logic 1 means that a time out error has been
detected. This bit is cleared by a RESET. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode
Register 2, 0xF1 in Serial Port Logical Device Configuration Registers) is 鈥?鈥? writing a one to this bit clears
the TMOUT status bit. Writing a zero to this bit has no effect. If the TIMEOUT_SELECT bit (bit 4 of the
SMSC LPC47M172
Page 91
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
DATASHEET

LPC47M172_07 PDF文件相關(guān)型號(hào)

LPC47M172-NW

LPC47M172_07相關(guān)型號(hào)PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號(hào)推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見(jiàn)，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見(jiàn)一經(jīng)采納，將有感恩紅包奉上哦！