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Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

The Parallel Port configuration registers are summarized in Table 11.2 in the 鈥淐onfiguration鈥?section. The

Parallel Port logical device configuration registers (0xF0 and 0xF1) are defined in Table 11.11.

The parallel port also incorporates SMSC鈥檚 ChiProtect circuitry, which prevents possible damage to the

parallel port due to printer power-up.

The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their

associated registers and control gating. The control and data port are read/write by the CPU, the status

port is read/write in the EPP mode. The address map of the Parallel Port is shown below:

DATA PORT

STATUS PORT

CONTROL PORT

EPP ADDR PORT

BASE ADDRESS + 00H

BASE ADDRESS + 01H

BASE ADDRESS + 02H

BASE ADDRESS + 03H

EPP DATA PORT 0

EPP DATA PORT 1

EPP DATA PORT 2

EPP DATA PORT 3

BASE ADDRESS + 04H

BASE ADDRESS + 05H

BASE ADDRESS + 06H

BASE ADDRESS + 07H

The bit map of these registers is:

D0

PD0

TMOUT

D1

PD1

0

D2

PD2

0

nINIT

PD2

PD2

PD2

PD2

PD2

D3

PD3

nERR

SLC

PD3

PD3

PD3

PD3

PD3

D4

PD4

SLCT

IRQE

PD4

PD4

PD4

PD4

PD4

D5

PD5

PE

PCD

PD5

PD5

PD5

PD5

PD5

D6

PD6

nACK

0

PD6

PD6

PD6

PD6

PD6

D7

NOTE

PD7

1

nBUSY

1

0

PD7

PD7

PD7

PD7

PD7

1

2

2

2

2

2

DATA PORT

STATUS

PORT

CONTROL

PORT

EPP ADDR

PORT

EPP DATA

PORT 0

EPP DATA

PORT 1

EPP DATA

PORT 2

EPP DATA

PORT 3

Note 1:

Note 2:

STROBE AUTOFD

PD0

PD0

PD0

PD0

PD0

PD1

PD1

PD1

PD1

PD1

These registers are available in all modes.

These registers are only available in EPP mode.

SMSC/Non-SMSC Register Sets (Rev.

01-11-07)

Page 90

SMSC LPC47M172

DATASHEET

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