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LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • SMSC   SMSC

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Note 1
Note 2
Note 3
Note 4
Note 5
Note 6
Note 7
Note 8
DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
This bit no longer has a pin associated with it.
When operating in the XT mode, this register is not available.
These bits are always zero in the non-FIFO mode.
Writing a one to this bit has no effect. DMA modes are not supported in this chip.
The UART1 and UART2 FCR鈥檚 are shadowed in the UART1 FIFO Control Shadow Register (runtime
register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21).
SMSC LPC47M172
Page 87
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
DATASHEET

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LPC47M172-NW

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