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LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • SMSC   SMSC

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 32 - Register Summary for an Individual UART Channel
REGISTER
ADDRESS
(Note 1)
REGISTER NAME
Receive Buffer Register (Read Only)
Transmitter Holding Register (Write Only)
Interrupt Enable Register
REGISTER
SYMBOL
RBR
THR
IER
BIT 0
Data Bit 0
(Note 2)
BIT 1
Data Bit 1
Data Bit 1
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETHREI)
Interrupt ID
Bit
RCVR FIFO
Reset
Word Length
Select Bit 1
(WLS1)
BIT 2
Data Bit 2
Data Bit 2
Enable
Receiver
Line Status
Interrupt
(ELSI)
BIT 3
Data Bit 3
Data Bit 3
Enable
MODEM
Status
Interrupt
(EMSI)
BIT 4
Data Bit 4
Data Bit 4
0
BIT 5
Data Bit 5
Data Bit 5
0
BIT 6
Data Bit 6
Data Bit 6
0
BIT 7
Data Bit 7
Data Bit 7
0
ADDR = 0
DLAB = 0
ADDR = 0
DLAB = 0
ADDR = 1
DLAB = 0
Data Bit 0
Enable
Received
Data
Available
Interrupt
(ERDAI)
鈥?鈥?if Interrupt
Pending
ADDR = 2
Interrupt Ident. Register (Read Only)
IIR
Interrupt ID
Bit
XMIT FIFO
Reset
Number of
Stop Bits
(STB)
OUT1
(Note 4)
Interrupt ID
Bit
(Note 6)
DMA Mode
Select
(Note 7)
0
0
FIFOs
Enabled
(Note 6)
FIFOs
Enabled
(Note 6)
ADDR = 2
FIFO Control Register (Write Only)
FCR
(Note 8)
FIFO Enable
Reserved
Reserved
RCVR Trigger RCVR
LSB
Trigger
MSB
Set Break
Divisor
Latch
Access Bit
(DLAB)
0
Error in
RCVR
FIFO
(Note 6)
ADDR = 3
Line Control Register
LCR
Word Length
Select Bit 0
(WLS0)
Parity
Enable
(PEN)
OUT2
(Note 4)
Even Parity
Select
(EPS)
Loop
Break
Interrupt
(BI)
Clear to
Send (CTS)
Stick Parity
ADDR = 4
ADDR = 5
MODEM Control Register
Line Status Register
MCR
LSR
Data Terminal Request to
Ready (DTR) Send (RTS)
Data Ready
(DR)
Overrun
Error (OE)
0
Transmitter
Holding
Register
(THRE)
Data Set
Ready
(DSR)
Bit 5
Bit 5
Bit 13
0
Transmitter
Empty
(TEMT)
(Note 3)
Parity Error
(PE)
Framing
Error (FE)
ADDR = 6
MODEM Status Register
MSR
Delta Clear to
Send (DCTS)
Delta Data
Set Ready
(DDSR)
Bit 1
Bit 1
Bit 9
ADDR = 7
ADDR = 0
DLAB = 1
ADDR = 1
DLAB = 1
Scratch Register
(Note 5)
Divisor Latch (LS)
Divisor Latch (MS)
SCR
DDL
DLM
Bit 0
Bit 0
Bit 8
Trailing
Edge Ring
Indicator
(TERI)
Bit 2
Bit 2
Bit 10
Delta Data
Carrier
Detect
(DDCD)
Bit 3
Bit 3
Bit 11
Ring Indicator
(RI)
Bit 4
Bit 4
Bit 12
Bit 6
Bit 6
Bit 14
Data
Carrier
Detect
(DCD)
Bit 7
Bit 7
Bit 15
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
Page 86
SMSC LPC47M172
DATASHEET

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