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LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • SMSC   SMSC

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Bit 0
Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the
last time the MSR was read.
Bit 1
Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time
the MSR was read.
Bit 2
Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic 鈥?鈥?to logic
鈥?鈥?
Bit 3
Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state.
Note:
Bit 4
This bit is the complement of the Clear To Send (nCTS) input. If bit 4 of the MCR is set to logic 鈥?鈥? this bit
is equivalent to nRTS in the MCR.
Bit 5
This bit is the complement of the Data Set Ready (nDSR) input. If bit 4 of the MCR is set to logic 鈥?鈥? this
bit is equivalent to DTR in the MCR.
Bit 6
This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic 鈥?鈥? this bit is
equivalent to OUT1 in the MCR.
Bit 7
This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic 鈥?鈥?
this bit is equivalent to OUT2 in the MCR.
Whenever bit 0, 1, 2, or 3 is set to a logic 鈥?鈥? a MODEM Status Interrupt is generated.
6.28.11 Scratchpad Register (SCR)
Address Offset =7H, DLAB =X, READ/WRITE
This 8 bit read/write register has no effect on the operation of the Serial Port.
scratchpad register to be used by the programmer to hold data temporarily.
It is intended as a
6.29
Programmable Baud Rate Generator (And Divisor Latches DLH,
DLL)
The Serial Port contains a programmable Baud Rate Generator that is capable of dividing the internal PLL
clock by any divisor from 1 to 65535. The internal PLL clock is divided down to generate a 1.8462MHz
frequency for Baud Rates less than 38.4k, a 1.8432MHz frequency for 115.2k, a 3.6864MHz frequency for
230.4k and a 7.3728MHz frequency for 460.8k. This output frequency of the Baud Rate Generator is 16x
the Baud rate. Two 8 bit latches store the divisor in 16 bit binary format. These Divisor Latches must be
loaded during initialization in order to insure desired operation of the Baud Rate Generator. Upon loading
either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This prevents long counts on
initial load. If a 0 is loaded into the BRG registers the output divides the clock by the number 3. If a 1 is
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
Page 82
SMSC LPC47M172
DATASHEET

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