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LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • SMSC   SMSC

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Bit 2
This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or
written by the CPU.
Bit 3
Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial port
interrupt output is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial port
interrupt outputs are enabled.
Bit 4
This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic
鈥?鈥? the following occur:
1.
2.
3.
4.
5.
6.
7.
The TXD is set to the Marking State(logic 鈥?鈥?.
The receiver Serial Input (RXD) is disconnected.
The output of the Transmitter Shift Register is 鈥渓ooped back鈥?into the Receiver Shift Register input.
All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected.
The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the
four MODEM Control inputs (nDSR, nCTS, RI, DCD).
The Modem Control output pins are forced inactive high.
Data that is transmitted is immediately received.
This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the
diagnostic mode, the receiver and the transmitter interrupts are fully operational. The MODEM Control
Interrupts are also operational but the interrupts鈥?sources are now the lower four bits of the MODEM
Control Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt
Enable Register.
Bits 5 through 7
These bits are permanently set to logic zero.
6.28.9 Line Status Register (LSR)
Address Offset = 5H, DLAB = X, READ/WRITE
Bit 0
Data Ready (DR). It is set to a logic 鈥?鈥?whenever a complete incoming character has been received and
transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic 鈥?鈥?by reading all of the
data in the Receive Buffer Register or the FIFO.
Bit 1
Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the next
character was transferred into the register, thereby destroying the previous character. In FIFO mode, an
overrun error will occur only when the FIFO is full and the next character has been completely received in
the shift register, the character in the shift register is overwritten but not transferred to the FIFO. The OE
indicator is set to a logic 鈥?鈥?immediately upon detection of an overrun condition, and reset whenever the
Line Status Register is read.
Bit 2
Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd
parity, as selected by the even parity select bit. The PE is set to a logic 鈥?鈥?upon detection of a parity error
and is reset to a logic 鈥?鈥?whenever the Line Status Register is read. In the FIFO mode this error is
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
Page 80
SMSC LPC47M172
DATASHEET

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