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LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • SMSC   SMSC

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
FIFO
MODE
ONLY
INTERRUPT
IDENTIFICATION
REGISTER
1
1
0
0
0
0
1
0
0
0
0
0
INTERRUPT SET AND RESET FUNCTIONS
No Characters
Have Been
Removed From or
Input to the
Character
Reading the
RCVR FIFO
Second
Timeout
Receiver Buffer
during the last 4
Indication
Register
Char times and
there is at least 1
char in it during
this time
Reading the IIR
Register (if
Transmitter
Transmitter
Source of
Holding
Third
Holding Register
Interrupt) or
Register
Empty
Writing the
Empty
Transmitter
Holding Register
Clear to Send or
Data Set Ready
Reading the
MODEM
Fourth
MODEM Status
or Ring Indicator
Status
or Data Carrier
Register
Detect
6.28.7 Line Control Register (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE
Start LSB Data 5-8 bits MSB Parity
Stop
Serial Data
This register contains the format information of the serial line. The bit definitions are:
Bits 0 and 1
These two bits specify the number of bits in each transmitted or received serial character. The encoding of
bits 0 and 1 is as follows:
The Start, Stop and Parity bits are not included in the word length.
BIT 1
0
0
1
1
Bit 2
This bit specifies the number of stop bits in each transmitted or received serial character. The following
table summarizes the information.
BIT 0
0
1
0
1
WORD LENGTH
5 Bits
6 Bits
7 Bits
8 Bits
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
Page 78
SMSC LPC47M172
DATASHEET

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