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LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • SMSC   SMSC

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
6.27
Enhanced DUMPREG
The DUMPREG command is designed to support system run-time diagnostics and application software
development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR
MODE command the eighth byte of the DUMPREG command has been modified to contain the additional
data from these two commands.
6.27.1 Compatibility
The LPC47M172 was designed with software compatibility in mind. It is a fully backwards- compatible
solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for
compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a
hardware reset of the FDC, all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2
Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the
system BIOS.
6.28
Serial Port (UART)
The LPC47M172 incorporates two full function UARTs. They are compatible with the 16450, the 16450
ACE registers and the 16C550A. The UARTs perform serial-to-parallel conversion on received characters
and parallel-to-serial conversion on transmit characters. The data rates are independently programmable
from 460.8K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop
bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs contain a programmable baud
rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The
UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration Registers for
information on disabling, power down and changing the base address of the UARTs. The interrupt from a
UART is enabled by programming OUT2 of that UART to a logic 鈥?鈥? OUT2 being a logic 鈥?鈥?disables that
UART鈥檚 interrupt. The second UART also supports IrDA, HP-SIR, and ASK-IR infrared modes of
operation.
Note:
Input pins of Serial Port 2 are internally pulled down to VSS only until Serial Port 2 is enabled. Once Serial
Port 2 is enabled, the pull-downs are removed until VTR POR.
6.28.1 Register Description
Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial
port is defined by the configuration registers (see 鈥淐onfiguration鈥?section). The Serial Port registers are
located at sequentially increasing addresses above these base addresses (see Table 6.28).
Table 6.28 - Addressing the Serial Port
DLAB*
0
0
0
X
X
X
X
X
X
A2
0
0
0
0
0
0
1
1
1
A1
0
0
0
1
1
1
0
0
1
A0
0
0
1
0
0
1
0
1
0
REGISTER NAME
Receive Buffer (read)
Transmit Buffer (write)
Interrupt Enable (read/write)
Interrupt Identification (read)
FIFO Control (write)
Line Control (read/write)
Modem Control (read/write)
Line Status (read/write)
Modem Status (read/write)
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
Page 74
SMSC LPC47M172
DATASHEET

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