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LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • 1113.49KB

  • SMSC   SMSC

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular
recording drives. This enhancement allows data transfers between Conventional and Perpendicular drives
without having to issue Perpendicular mode commands between the accesses of the different drive types,
nor having to change write pre-compensation values.
When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to
鈥?鈥?(Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to 鈥?鈥?for that
drive to be set automatically to Perpendicular mode. In this mode the following set of conditions also
apply:
1.
2.
3.
Note:
The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed
data rate.
The write pre-compensation given to a perpendicular mode drive will be 0ns.
For D0-D3 programmed to 鈥?鈥?for conventional mode drives any data written will be at the currently
programmed write pre-compensation.
Bits D0-D3 can only be overwritten when OW is programmed as a 鈥?鈥?If either GAP or WGATE is a 鈥?鈥?/div>
then D0-D3 are ignored.
Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND:
鈥淪oftware鈥?resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to 鈥?鈥? D0-D3
are unaffected and retain their previous value.
鈥淗ardware鈥?resets will clear all bits (GAP, WGATE and D0-D3) to 鈥?鈥? i.e all conventional mode.
Table 6.27 - Effects of WGATE and GAP Bits
LENGTH OF
GAP2 FORMAT
FIELD
22 Bytes
22 Bytes
22 Bytes
41 Bytes
PORTION OF
GAP 2
WRITTEN BY
WRITE DATA
OPERATION
0 Bytes
19 Bytes
0 Bytes
38 Bytes
WGATE
GAP
MODE
0
0
1
1
0
1
0
1
Conventional
Perpendicular
(500 Kbps)
Reserved
(Conventional)
Perpendicular
(1 Mbps)
6.26
Lock
In order to protect systems with long DMA latencies against older application software that can disable the
FIFO the LOCK Command has been added. This command should only be used by the FDC routines,
and application software should refrain from using it. If an application calls for the FIFO to be disabled
then the CONFIGURE command should be used.
The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the
CONFIGURE command can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic
鈥?鈥?all subsequent 鈥渟oftware RESETS by the DOR and DSR registers will not change the previously set
parameters to their default values. All 鈥渉ardware鈥?RESET from the nPCI_RESET pin will set the LOCK bit
to logic 鈥?鈥?and return the EFIFO, FIFOTHR, and PRETRK to their default values. A status byte is
returned immediately after issuing a LOCK command. This byte reflects the value of the LOCK bit set by
the command byte.
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
Page 73
SMSC LPC47M172
DATASHEET

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