最新免费av在线观看,亚洲综合一区成人在线,中文字幕精品无码一区二区三区,中文人妻av高清一区二区,中文字幕乱偷无码av先锋

LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • SMSC   SMSC

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預覽

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
6.7
Controller Phases
For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and
Result. Each phase is described in the following sections.
6.7.1
Command Phase
After a reset, the FDC enters the command phase and is ready to accept a command from the host. For
each of the commands, a defined set of command code bytes and parameter bytes has to be written to the
FDC before the command phase is complete. (Please refer to section 6.10 Command Set/Descriptions).
These bytes of data must be transferred in the order prescribed.
Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register.
RQM and DIO must be equal to 鈥?鈥?and 鈥?鈥?respectively before command bytes may be written. RQM is
set false by the FDC after each write cycle until the received byte is processed. The FDC asserts RQM
again to request each parameter byte of the command unless an illegal command condition is detected.
After the last parameter byte is received, RQM remains 鈥?鈥?and the FDC automatically enters the next
phase as defined by the command definition.
The FIFO is disabled during the command phase to provide for the proper handling of the 鈥淚nvalid
Command鈥?condition.
6.7.2
Execution Phase
All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA mode
as indicated in the Specify command.
After a reset, the FIFO is disabled. Each data byte is transferred by a read/write or DMA cycle depending
on the DMA mode. The Configure command can enable the FIFO and set the FIFO threshold value.
The following paragraphs detail the operation of the FIFO flow control. In these descriptions, <threshold>
is defined as the number of bytes available to the FDC when service is requested from the host and
ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to
15.
A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster
servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until
empty (full), then the transfer request goes inactive. The host must be very responsive to the service
request. This is the desired case for use with a 鈥渇ast鈥?system.
A high value of threshold (i.e. 12) is used with a 鈥渟luggish鈥?system by affording a long latency period after a
service request, but results in more frequent service requests.
Non-DMA Mode - Transfers from the FIFO to the Host
This part does not support non-DMA mode.
Non-DMA Mode - Transfers from the Host to the FIFO
This part does not support non-DMA mode.
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
Page 52
SMSC LPC47M172
DATASHEET

LPC47M172_07 PDF文件相關型號

LPC47M172-NW

LPC47M172_07相關型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務：
賣家服務：
技術客服：

0571-85317607

網(wǎng)站技術支持

13606545031

客服在線時間周一至周五
9:00-17:30

關注官方微信號，
第一時間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！