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LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • 1113.49KB

  • SMSC   SMSC

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
BITS 0 鈥?1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 6.8 for the settings corresponding to the
individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps
after a hardware reset.
BIT 2 NOPREC
This bit reflects the value of NOPREC bit set in the CCR register.
BIT 3 DMAEN
This bit reflects the value of DMAEN bit set in the DOR register bit 3.
BITS 4 鈥?6 UNDEFINED
Always read as a logic 鈥?鈥?/div>
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force Disk Change Register (see Power Control/Runtime Register Block runtime
register at offset 0x18).
6.4.11 Configuration Control Register (CCR)
Address 3F7 WRITE ONLY
PC/AT and PS/2 Modes
7
0
RESET
COND.
N/A
6
0
N/A
5
0
N/A
4
0
N/A
3
0
N/A
2
0
N/A
1
DRATE
SEL1
1
0
DRATE
SEL0
0
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 6.8 for the appropriate values.
BIT 2 鈥?7 RESERVED
Should be set to a logical 鈥?鈥?/div>
PS/2 Model 30 Mode
7
0
RESET
COND.
N/A
6
0
N/A
5
0
N/A
4
0
N/A
3
0
N/A
2
1
NOPREC DRATE
SEL1
N/A
1
0
DRATE
SEL0
0
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 6.8 for the appropriate values.
BIT 2 NO PRECOMPENSATION
This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in
Model 30 register mode. Unaffected by software reset.
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
Page 48
SMSC LPC47M172
DATASHEET

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