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LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • SMSC   SMSC

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
6.4.10 Digital Input Register (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
PC-AT Mode
7
DSK
CHG
N/A
6
0
N/A
5
0
N/A
4
0
N/A
3
0
N/A
2
0
N/A
1
0
N/A
0
0
N/A
RESET
COND.
BIT 0 鈥?6 UNDEFINED
The data bus outputs D0 鈥?6 are read as 鈥?鈥?
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force Disk Change Register (see Power Control/Runtime Register Block runtime
register at offset 0x18).
PS/2 Mode
7
DSK
CHG
N/A
6
1
N/A
5
1
N/A
4
1
N/A
3
1
N/A
2
DRATE
SEL1
N/A
1
DRATE
SEL0
N/A
0
nHIGH
DENS
1
RESET
COND.
BIT 0 nHIGH DENS
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and
300 Kbps are selected.
BITS 1 鈥?2 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 6.8 for the settings corresponding to the
individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250
Kbps after a hardware reset.
BITS 3 鈥?6 UNDEFINED
Always read as a logic 鈥?鈥?/div>
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force Disk Change Register (see Power Control/Runtime Register Block runtime
register at offset 0x18).
Model 30 Mode
7
DSK CHG
RESET
COND.
N/A
6
0
0
5
0
0
4
0
0
3
2
1
DMAEN NOPREC DRATE
SEL1
0
0
1
0
DRATE
SEL0
0
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
Page 47
SMSC LPC47M172
DATASHEET

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