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LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • SMSC   SMSC

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 6.7 - Precompensation Delays
PRECOMP
432
111
001
010
011
100
101
110
000
BIT 5 UNDEFINED
Should be written as a logic 鈥?鈥?
BIT 6 LOW POWER
A logic 鈥?鈥?written to this bit will put the floppy controller into manual low power mode. The floppy
controller clock and data separator circuits will be turned off. The controller will come out of manual low
power mode after a software reset or access to the Data Register or Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self
clearing.
Separator circuits will be turned off. The controller will come out of manual low power.
Note:
The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x19 in the
Power Control/Runtime Register block.
Table 6.8 - Data Rates
DRIVE RATE
DRT1
0
0
0
0
0
0
0
0
1
1
1
1
DRT0
0
0
0
0
1
1
1
1
0
0
0
0
DATA RATE
SEL1
1
0
0
1
1
0
0
1
1
0
0
1
SEL0
1
0
1
0
1
0
1
0
1
0
1
0
DATA RATE
MFM
1Meg
500
300
250
1Meg
500
500
250
1Meg
500
2Meg
250
FM
---
250
150
125
---
250
250
125
---
250
---
125
1
1
0
0
1
1
0
0
1
1
0
0
DENSEL
DRATE(1)
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
PRECOMPENSATION
DELAY (NSEC)
<2Mbps
2Mbps
0
0.00
20.8
41.67
41.7
83.34
62.5
125.00
83.3
166.67
104.2
208.33
125
250.00
Default
Default
Default: See Table 6.10
Note 1:
00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
01 = 3-Mode Drive
10 = 2 Meg Tape
The DRATE and DENSEL values are mapped onto the DRVDEN pins.
Page 44
SMSC LPC47M172
Drive Rate Table (Recommended)
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
DATASHEET

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