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Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

Table 6.4 - Internal 2 Drive Decode - Drives 0 and 1 Swapped

DIGITAL OUTPUT

REGISTER

Bit 5

X

1

0

Bit 4

1

X

0

Bit1

0

0

X

Bit 0

0

1

X

DRIVE SELECT OUTPUTS

(ACTIVE LOW)

nDS1

0

1

1

nDS0

1

0

1

MOTOR ON OUTPUTS

(ACTIVE LOW)

nMTR1

nMTR0

nBIT 4

nBIT 5

nBIT 4

nBIT 5

nBIT 4

nBIT 5

BIT 6 MOTOR ENABLE 2

The MTR2 disk interface output is not supported in the LPC47M172.

BIT 7 MOTOR ENABLE 3

The MTR3 disk interface output is not supported in the LPC47M172.

6.4.6

Tape Drive Register (TDR)

Address 3F3 READ/WRITE

The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign

tape support to a particular drive during initialization. Any future references to that drive automatically

invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 6.5

illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape

support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is

unaffected by a software reset.

Table 6.5 - Tape Select Bits

TAPE SEL1

(TDR.1)

0

0

1

1

TAPE SEL0

(TDR.0)

0

1

0

1

DRIVE

SELECTED

None

1

2

3

Normal Floppy Mode

Normal mode.Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 鈥?7 are 鈥?鈥?

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

0

DB1

tape sel1

DB0

tape sel0

REG 3F3

Enhanced Floppy Mode 2 (OS2)

Register 3F3 for Enhanced Floppy Mode 2 operation.

DB7

DB6

REG 3F3 Reserved Reserved

DB5

DB4

Drive Type ID

DB3

DB2

Floppy Boot Drive

DB1

tape sel1

DB0

tape sel0

SMSC/Non-SMSC Register Sets (Rev.

01-11-07)

Page 42

SMSC LPC47M172

DATASHEET

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