LPC47M172_07 Datasheet

IC型號：
LPC47M172_07
PDF描述：
SMSC Corporation [Advanced I/O Controller with Motherboard ...
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芯片廠家：
SMSC

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Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

6.4.5

Digital Output Register (DOR)

Address 3F2 READ/WRITE

The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the

enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software

reset. The DOR can be written to at any time.

MOT

EN3

MOT

EN2

MOT

EN1

MOT

EN0

DMAEN

nRESET

DRIVE

SEL1

DRIVE

SEL0

RESET

COND.

BIT 0 and 1 DRIVE SELECT

These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at

one time.

BIT 2 nRESET

A logic 鈥?鈥?written to this bit resets the Floppy disk controller. This reset will remain active until a logic 鈥?鈥?/div>

is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the

other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by

consecutive writes to this register is a valid method of issuing a software reset.

BIT 3 DMAEN

PC/AT and Model 30 Mode:

Writing this bit to logic 鈥?鈥?will enable the DMA and interrupt functions. This bit being a logic 鈥?鈥?will disable

the DMA and interrupt functions. This bit is a logic 鈥?鈥?after a reset and in these modes.

PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will

be cleared to a logic 鈥?鈥?

BIT 4 MOTOR ENABLE 0

This bit controls the MTR0 disk interface output. A logic 鈥?鈥?in this bit will cause the output pin to go active.

BIT 5 MOTOR ENABLE 1

This bit controls the MTR1 disk interface output. A logic 鈥?鈥?in this bit will cause the output pin to go active.

DRIVE

DOR VALUE

1CH

2DH

Table 6.3 - Internal 2 Drive Decode - Normal

DIGITAL OUTPUT

Bit 5

Bit 4

Bit1

Bit 0

DRIVE SELECT OUTPUTS

(ACTIVE LOW)

nDS1

nDS0

MOTOR ON OUTPUTS

(ACTIVE LOW)

nMTR1

nMTR0

nBIT 5

nBIT 4

nBIT 5

nBIT 4

nBIT 5

nBIT 4

SMSC/Non-SMSC Register Sets (Rev.

01-11-07)

Page 41

SMSC LPC47M172

DATASHEET

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