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LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • SMSC   SMSC

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
BIT 1 WRITE PROTECT
Active high status of the WRITE PROTECT disk interface input. A logic 鈥?鈥?indicates that the disk is write
protected.
BIT 2 INDEX
Active high status of the INDEX disk interface input.
BIT 3 HEAD SELECT
Active low status of the HDSEL disk interface input. A logic 鈥?鈥?selects side 1 and a logic 鈥?鈥?selects side
0.
BIT 4 TRACK 0
Active high status of the TRK0 disk interface input.
BIT 5 STEP
Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output
going active, and is cleared with a read from the DIR register, or with a hardware or software reset.
BIT 6 DMA REQUEST
Active high status of the DMA request pending.
BIT 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy Disk Interrupt.
6.4.4
Status Register B (SRB)
Address 3F1 READ ONLY
This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30
modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins
D0 鈥?D7 are held in a high impedance state for a read of address 3F1.
PS/2 Mode
7
1
RESET
COND.
BIT 0 MOTOR ENABLE 0
Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and
unaffected by a software reset.
BIT 1 MOTOR ENABLE 1
Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and
unaffected by a software reset.
BIT 2 WRITE GATE
Active high status of the WGATE disk interface output.
1
6
1
1
5
DRIVE
SEL0
0
4
3
2
WDATA RDATA WGATE
TOGGLE TOGGLE
0
0
0
1
MOT
EN1
0
0
MOT
EN0
0
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
Page 39
SMSC LPC47M172
DATASHEET

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