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LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • 1113.49KB

  • SMSC   SMSC

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
6.2
Host Processor Interface (LPC)
The host processor communicates with the LPC47M172 through a series of read/write registers via the
LPC interface. The port addresses for these registers are shown in Table 6.1. Register access is
accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide.
6.3
LPC Interface
The following sub-sections specify the implementation of the LPC bus.
6.3.1
LPC Interface Signal Definition
The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI
33MHz electrical signal characteristics.
SIGNAL
NAME
LAD[3:0]
nLFRAME
nPCI_RESET
nLDRQ
nIO_PME
nLPCPD
SER_IRQ
PCI_CLK
Note:
TYPE
I/O
Input
Input
Output
OD
Input
I/O
Input
DESCRIPTION
LPC address/data bus. Multiplexed command, address and data bus.
Frame signal. Indicates start of new cycle and termination of broken cycle
PCI Reset. Used as LPC Interface Reset.
Encoded DMA/Bus Master request for the LPC interface.
Power Mgt Event signal. Allows the LPC47M172 to request wakeup.
Powerdown Signal. Indicates that the LPC47M172 should prepare for power to be shut
on the LPC interface.
Serial IRQ.
PCI Clock.
The CLKRUN# signal is not implemented in this part.
6.3.2
LPC Cycles
The following cycle types are supported by the LPC protocol.
CYCLE TYPE
I/O Write
I/O Read
DMA Write
DMA Read
1 Byte
1 Byte
1 Byte
1 Byte
TRANSFER SIZE
LPC47M172 ignores cycles that it does not support.
6.3.3
Field Definitions
The data transfers are based on specific fields that are used in various combinations, depending on the
cycle type. These fields are driven onto the LAD[3:0] signal lines to communicate address, control and
data information over the LPC bus between the host and the LPC47M172. See the
Low Pin Count (LPC)
Interface Specification
Revision 1.0 from Intel, Section 4.2 for definition of these fields.
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
Page 33
SMSC LPC47M172
DATASHEET

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