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LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • SMSC   SMSC

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Bit 0 controls the source of the 32kHz (nominal) clock for the nFPRST debounce circuitry, the LED blink
logic and the 鈥渨ake on specific key鈥?logic. When the external 32kHz clock is connected, that will be the
source for the nFPRST debounce circuitry, LED and 鈥渨ake on specific key鈥?logic. When the external
32kHz clock is not connected, an internal 32kHz clock source will be derived from the 14MHz clock for the
鈥渨ake on specific key鈥?logic. The nFPRST debounce circuitry and LED require the 32kHz clock be always
connected.
The 鈥渨ake on specific key鈥?function will not work under VTR power (VCC removed) if the external 32kHz
clock is not connected. It will work under VCC power even if the external 32 kHz clock is not connected.
5.6
14.318 MHz Clock Input
The LPC47M172 utilizes a 14.318 MHz clock input (CLOCKI). This clock is used to generate specific
clocks needed for various logic (including SIO functions, Fan Tachometer, etc.) in the LPC47M172. The
CLOCKI is powered by VCC and is not available in VTR power only (VCC=0).
5.7
Internal PWRGOOD
An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the
host interface as VCC cycles on and off. When the internal PWRGOOD signal is 鈥?鈥?(active), VCC > 2.3V
(nominal), and the LPC47M172 host interface is active. When the internal PWRGOOD signal is 鈥?鈥?/div>
(inactive), VCC <= 2.3V (nominal), and the LPC47M172 host interface is inactive; that is, LPC bus reads
and writes will not be decoded.
The LPC47M172 device pins nIO_PME, CLOCKI32, KDAT, MDAT, nRI1, nRI2, and most GPIOs (as input)
are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive,
provided VTR is powered. Other VTR powered pins listed in Table 3.1 also remain active when the
internal PWRGOOD signal has gone inactive, provided VTR is powered. See Trickle Power Functionality
section.
5.8
Maximum Current Values
See the 鈥淥perational Description鈥?section for the maximum current values.
The maximum VTR current, I
TR
, is given with all outputs open (not loaded), and all inputs transitioning
from/to 0V to/from 3.3V. The total maximum current for the part is the unloaded value PLUS the maximum
current sourced by the pin that is driven by VTR. The pins that are powered by VTR are listed in the Table
3.1. The push-pull capable outputs will source minimum current specified in Table 12.2 at 2.4V when
driving.
The maximum VCC current, I
CC
, is given with all outputs open (not loaded) and all inputs transitioning
from/to 0V to/from 3.3V.
5.9
Power Management Events (PME/SCI)
The LPC47M172 offers support for Power Management Events (PMEs), also referred to as System
Control Interrupt (SCI) events. The terms PME and SCI are used synonymously throughout this document
to refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal. See the
鈥淧ME Support鈥?section.
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
Page 31
SMSC LPC47M172
DATASHEET

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