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LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • SMSC   SMSC

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PIN#
106,
108,
109
111
NAME
(NOTE 1)
GP13-GP15
DESCRIPTION
General Purpose I/O. GPIO can be
configured as an open-drain output.
General Purpose I/O. GPIO can be
configured as an open-drain output.
Fan Tachometer 1 Input
General Purpose I/O. GPIO can be
configured as an open-drain output.
Fan Tachometer 2 Input
TEST (1)
Test Enable Input for XOR-Chain test 鈥?/div>
the external pull-up or internal pull-down
sets the strap value. The XOR output is
the nDTR1 pin.
NO CONNECT (1)
See Note11
No Connect
BUFFER
NAME
(NOTE 2)
IO8
PWR
WELL
(NOTE 3)
VTR
NOTES
6
GP16/
FAN_TACH1
GP17/
FAN_TACH2
IO8
VTR
6
112
IO8
VTR
6
98
TEST_EN
IPD
VTR
117
Note 1:
NC
IPD
-
11
The 鈥渘鈥?as the first letter of a signal name or the 鈥?鈥?as the suffix of a signal name indicates an 鈥淎ctive Low鈥?/div>
signal. The primary and secondary functions on the pins are separated by 鈥?鈥?
The buffer names are described in the 鈥淏uffer Name Descriptions鈥?section.
Open-drain pins should be pulled-up externally to supply shown in the power well column. The
nIDE_RSTDRV, nHD_LED, DDCSDA_5V and DDCSCL_5V open-drain pins require external pull-ups to
VCC5V. The nBACKFEED_CUT, SCK_BJT_GATE and nPS_ON open-drain pins require external pull-
ups to V_5P0_STBY. Inputs with internal pull-ups are pulled internally to the supply shown in the power
well column. All other pins are driven under the power well shown. See the 鈥淧ins With Internal Resistors鈥?
鈥淧ins That Require External Resistors鈥?and 鈥淒efault State of Pins鈥?sections.
The 32.768 kHz input clock must not be driven high when VTR = 0V. CLOCKI32 is clock source to various
logic in the part, including LED, 鈥渨ake on specific key鈥?and nFPRST debounce circuitry. The 32 KHz input
clock must always be connected. There is a bit in the configuration register at 0xF0 in Logical Device A
that indicates whether or not the 32KHz clock is connected. This bit determines the clock source for the
logic. This bit must always be set to 鈥?鈥?(鈥?鈥?32 KHz clock connected; reset default=鈥?鈥?.
The nLPCPD pin may be tied high. The LPC interface will function properly if the nPCI_RESET signal
follows the protocol defined for the nLRESET signal in the 鈥淟ow Pin Count Interface Specification鈥?
However, if nLPCPD is tied high, the keyboard wakeup isolation logic will be affected.
These pins (except DDC and FAN_TACH functions) are also inputs to VTR powered logic internal to the
part. If DDC and FAN_TACH functions are selected on GPIOs, the pins will tri-state when VCC power is
removed.
External pullups must be placed on the nKBDRST and GA20M pins. If the nKBDRST and GA20M
functions are to be used, the system must ensure that these pins are high. See the 鈥淭hat Require External
Resistors鈥?section.
When DDC functions are selected on GP20-GP23, the pins become IO_SW type and require external pull-
ups to the appropriate voltages. See the 鈥淭hat Require External Resistors鈥?section. When the GPIO
functions are selected, the pins are IS0D8.
The IRTX2 pin is driven low upon power-up of VCC. This pin will remain low following a power-up (VCC
POR) until it is selected via the IR MUX bits and serial port 2 is enabled by setting the activate bit, at which
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
Page 21
SMSC LPC47M172
DATASHEET

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