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LPC47M172_07 Datasheet

  • LPC47M172_07

  • SMSC Corporation [Advanced I/O Controller with Motherboard ...

  • 1113.49KB

  • SMSC   SMSC

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PIN#
16
NAME
(NOTE 1)
nSTEP
DESCRIPTION
17
nDIR
18
19
20
nDS0
nMTR0
nINDEX
21
DRVDEN1
22
DRVDEN0
23
nDCD1
24
nDSR1
25
RXD1
Step Pulse Output. This active low high
current driver issues a low pulse for each
track-to-track movement of the head.
Can be configured as an Open-Drain
Output.
O12
Step Direction Output. This high current
low active output determines the direction
of the head movement. A logic 鈥?鈥?on this
pin means outward motion, while a logic
鈥?鈥?means inward motion. Can be
configured as an Open-Drain Output.
O12
Drive Select 0 Output. Can be configured
as an Open-Drain Output.
Motor On 0 Output. Can be configured as O12
an Open-Drain Output.
IS
This active low Schmitt Trigger input
senses from the disk drive that the head
is positioned over the beginning of a
track, as marked by an index hole.
O12
Drive Density Select 1 Output. Indicates
the drive and media selected. Can be
configured as Open-Drain Output.
O12
Drive Density Select 0 Output. Indicates
the drive and media selected. Can be
configured as Open-Drain Output.
SERIAL PORT 1 INTERFACE (8)
I
Active low Data Carrier Detect input for
the serial port. Handshake signal that
notifies the UART that carrier signal is
detected by the modem. The CPU can
monitor the status of nDCD signal by
reading bit 7 of Modem Status Register
(MSR). A nDCD signal state change from
low to high after the last MSR read will set
MSR bit 3 to a 1. If bit 3 of Interrupt
Enable Register is set, the interrupt is
generated when nDCD changes state.
Note: Bit 7 of MSR is the complement of
nDCD.
I
Active low Data Set Ready input for the
serial port. Handshake signal that notifies
the UART that the modem is ready to
establish the communication link. The
CPU can monitor the status of nDSR
signal by reading bit 5 of Modem Status
Register (MSR). A nDSR signal state
change from low to high after the last
MSR read will set MSR bit 1 to a 1. If bit
3 of Interrupt Enable Register is set, the
interrupt is generated when nDSR
changes state.
Note: Bit 5 of MSR is the complement of
nDSR.
Receiver serial data input.
IS
Page 16
BUFFER
NAME
(NOTE 2)
O12
PWR
WELL
(NOTE 3)
VCC
NOTES
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SMSC LPC47M172
SMSC/Non-SMSC Register Sets (Rev.
01-11-07)
DATASHEET

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