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Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

Chapter 3

Description of Pin Functions

Table 3.1 - LPC47M172 Pin Description

PIN#

NAME

(NOTE 1)

DESCRIPTION

BUFFER

NAME

(NOTE 2)

PWR

WELL

(NOTE 3)

NOTES

POWER AND GROUND PINS (20)

See Note 11

6,31,

49,60,

123

76,93,

107,

117

See Note

VCC

+3.3 Volt Main Supply Voltage (5)

PWR

VTR

+3.3 Volt Standby Supply Voltage (4)

See

Note

PWR

11

71

8,29,

46,58,

78,96,

110

70

72

V_5P0_STBY

VSS

+5 Volt Standby Supply Voltage.

Ground (7)

PWR

PWR

REF5V

REF5V_STBY

97

F_CAP

65

91

52

CLOCKI

CLOCKI32

nLPCPD

53

SER_IRQ

54

nLDRQ

55

56

57,59,

61,62

PCI_CLK

nLFRAME

LAD[3:0]

AO

5V Reference Output. Requires external

pull-up to VCC5V.

AO

Highest System Standby Voltage.

Requires external pull-up to

V_5P0_STBY.

Internal Regulator Filter Capacitor. This

pin is a no connect. A filter capacitor can

be placed on this pin if it is required by

system board layout.

CLOCKS (2)

14.318Mhz Clock Input

IS

32.768kHz Clock Input

IS

PROCESSOR/HOST LPC INTERFACE (11)

PCI_I

Active low input Power Down signal

indicates that the LPC47M172 should

prepare for power to be shut-off on the

LPC interface.

Serial IRQ pin used with the PCI_CLK pin PCI_IO

to transfer LPC47M172 interrupts to the

host.

PCI_O

Active low output used for encoded

DMA/Bus Master request for the LPC

interface.

33.33 MHz PCI Clock input.

PCI_ICLK

PCI_I

Active low input indicates start of new

cycle and termination of broken cycle.

PCI_IO

Active high LPC I/O used for multiplexed

command, address and data bus.

VCC

VTR

VCC

VTR

VCC

4

5

VCC

VCC

VCC

VCC

VCC

SMSC/Non-SMSC Register Sets (Rev.

01-11-07)

Page 14

SMSC LPC47M172

DATASHEET

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