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CAT1024LI-25T3 Datasheet

  • CAT1024LI-25T3

  • Catalyst Semiconductor [Supervisory Circuits with I2C Seria...

  • CATALYST

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CAT1024, CAT1025
DEVICE OPERATION
Reset Controller Description
The CAT1024/25 precision RESET controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with open
drain RESET outputs.
During power-up, the RESET outputs remain active
until V
CC
reaches the V
TH
threshold and will continue
driving the outputs for approximately 200ms (t
PURST
)
after reaching V
TH
. After the t
PURST
timeout interval, the
device will cease to drive the reset outputs. At this
point the reset outputs will be pulled up or down by
their respective pull up/down resistors.
During power-down, the RESET outputs will be active
爐爐爐爐爐爐
when V
CC
falls below V
TH
. The RESET output will be
valid so long as V
CC
is >1.0V (V
RVALID
). The device is
designed to ignore the fast negative going V
CC
transi-
ent pulses (glitches).
Reset output timing is shown in Figure 1.
Manual Reset Operation
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The RESET pin can operate as reset output and
manual reset input. The input is edge triggered; that
爐爐爐爐爐爐
is, the RESET input will initiate a reset timeout after
detecting a high to low transition.
爐爐爐爐爐爐
When RESET I/O is driven to the active state, the
200ms timer will begin to time the reset interval. If
external reset is shorter than 200ms, Reset outputs
will remain active at least 200ms.
The CAT1024/25 also have a separate manual reset
input. Driving the 爐爐爐 input low by connecting a
MR
pushbutton (normally open) from 爐爐爐 pin to GND will
MR
generate a reset condition. The input has an internal
pull up resistor.
Reset remains asserted while 爐爐爐 is low and for the
MR
Reset Timeout period after 爐爐爐 input has gone high.
MR
Glitches shorter than 100ns on 爐爐爐 input will not ge-
MR
nerate a reset pulse. No external debouncing circuits
are required. Manual reset operation using 爐爐爐 input
MR
is shown in Figure 2.
Hardware Data Protection
The CAT1024/25 supervisors have been designed to
solve many of the data corruption issues that have long
been associated with serial EEPROMs. Data corruption
occurs when incorrect data is stored in a memory
location which is assumed to hold correct data.
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output(s) are
active, in progress communications to the EEPROM
are aborted and no new communications are allowed.
In this condition an internal write cycle to the memory
can not be started, but an in progress internal non-
volatile memory write cycle can not be aborted. An
internal write cycle initiated before the Reset condition
can be successfully finished if there is enough time
(5ms) before V
CC
reaches the minimum value of 2V.
In addition, the CAT1025 includes a Write Protection
Input which when tied to V
CC
will disable any write
operations to the device.
漏 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. 3008 Rev. N

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