systems. A 2k-bit serial EEPROM memory and a
are integrated together in low power CMOS techno鈥?/div>
logy. Memory interface is via a 400kHz I
2
C bus.
The CAT1025 provides a precision V
CC
sense circuit
and two open drain outputs: one (RESET) drives high
爐爐爐爐爐爐
and the other (RESET) drives low whenever V
CC
falls
below the reset threshold voltage. The CAT1025 also
has a Write Protect input (WP). Write operations are
disabled if WP is connected to a logic high.
The CAT1024 also provides a precision V
CC
sense
爐爐爐爐爐爐
circuit, but has only a RESET output and does not
have a Write Protect input.
The power supply monitor and reset circuit protect
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 200 ms after the supply
voltage exceeds the reset threshold level. With both
active high and low reset signals, interface to
microcontrollers and other ICs is simple. In addition,
爐爐爐爐爐爐
the RESET pin or a separate input, 爐爐爐, can be used
MR
as an input for push-button manual reset capability.
The CAT1024/25 memory features a 16-byte page. In
addition, hardware data protection is provided by a
V
CC
sense circuit that prevents writes to memory
whenever V
CC
falls below the reset threshold or until
V
CC
reaches the reset threshold during power up.
Available packages include an 8-pin DIP and a
surface mount 8-pin SO, 8-pin TSSOP, 8-pin TDFN
and 8-pin MSOP packages. The TDFN package thick-
ness is 0.8mm maximum. TDFN footprint is 3x3mm.
For Ordering Information details, see page 19.
漏 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 3008 Rev. N