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ADIS16003 Datasheet

  • ADIS16003

  • Dual-Axis ±1.7 g Accelerometer with SPI Interface

  • 653.16KB

  • 17頁

  • AD

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ADIS16003
TIMING SPECIFICATIONS
T
A
= 鈥?0擄C to +125擄C, acceleration = 0
g,
unless otherwise noted.
Table 2.
Parameter
1, 2
f
SCLK 3
t
CONVERT
t
ACQ
t
1
t
2 4
t
34
t
4
t
5
t
6
t
7
t
8 5
t
9
1
V
CC
= 3.3
10
2
14.5 t
SCLK
1.5 t
SCLK
10
60
100
20
20
0.4 脳 t
SCLK
0.4 脳 t
SCLK
80
5
V
CC
= 5
10
2
14.5 t
CSLK
1.5 t
SCLK
10
30
75
20
20
0.4 x t
SCLK
0.4 x t
SCLK
80
5
Unit
kHz min
MHz max
Description
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
渭s typ
Throughput time = t
CONVERT
+ t
ACQ
= 16 t
SCLK
TCS/CS to SCLK setup time
Delay from TCS/CS until DOUT three-state disabled
Data access time after SCLK falling edge
Data setup time prior to SCLK rising edge
Data hold time after SCLK rising edge
SCLK high pulse width
SCLK low pulse width
TCS/CS rising edge to DOUT high impedance
Power-up time from shutdown
Guaranteed by design. All input signals are specified with tr and tf = 5 ns (10% to 90% of V
CC
) and timed from a voltage level of 1.6 V. The 3.3 V operating range spans
from 3.0 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2
See Figure 3 and Figure 4.
3
Mark/space ratio for the SCLK input is 40/60 to 60/40.
4
Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.4 V or 2.0 V with V
CC
= 3.3 V and time for an output to cross 0.8 V or
2.4 V with V
CC
= 5.0 V.
5
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Rev. 0 | Page 4 of 16

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