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ISL6537 Datasheet

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ISL6537
OSC
PWM
COMPARATOR
鈭哣
OSC
DRIVER
V
IN
L
O
DRIVER
PHASE
C
O
V
DDQ
Compensation Break Frequency Equations
1
F
Z1
= -----------------------------------
-
2蟺 x R
2
x C
1
1
F
Z2
= ------------------------------------------------------
-
2蟺 x
(
R
1
+ R
3
)
x C
3
1
F
P1
= --------------------------------------------------------
-
錚?/div>
C
1
x C
2
錚?/div>
-
2蟺 x R
2
x
錚?/div>
---------------------
錚?/div>
錚?/div>
C
1
+ C
2
錚?/div>
1
-
F
P2
= -----------------------------------
2蟺 x R
3
x C
3
-
+
Z
FB
V
E/A
+
ESR
(PARASITIC)
-
Z
IN
REFERENCE
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
C
1
C
2
R
2
Z
FB
Z
IN
C
3
R
1
R
3
V
DDQ
COMP
-
+
FB
R
4
Figure 4 shows an asymptotic plot of the DC-DC converter鈥檚
gain vs. frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 6. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F
P2
with the
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the graph of Figure 4 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
ISL6537
REFERENCE
R
1
錚?/div>
錚?/div>
V
DDQ
= 0.8
脳 錚?/div>
1 + ------
錚?/div>
-
R
4
錚?/div>
錚?/div>
FIGURE 3. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
100
80
F
Z1
F
Z2
F
P1
F
P2
OPEN LOOP
ERROR AMP GAIN
Modulator Break Frequency Equations
GAIN (dB)
60
40
20
0
-20
-40
-60
10
100
1K
MODULATOR
GAIN
F
LC
10K
F
ESR
100K
20LOG
(R
2
/R
1
)
1
-
F LC
= ------------------------------------------
2蟺
x
L O
x
C O
1
-
F ESR
= -------------------------------------------
2蟺
x
ESR
x
C O
The compensation network consists of the error amplifier
(internal to the ISL6537) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180 degrees. The equations below relate the compensation
network鈥檚 poles, zeros and gain to the components (R
1
, R
2
,
R
3
, C
1
, C
2
, and C
3
) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R
2
/R
1
) for desired converter bandwidth.
2. Place 1
ST
Zero Below Filter鈥檚 Double Pole (~75% F
LC
).
3. Place 2
ND
Zero at Filter鈥檚 Double Pole.
4. Place 1
ST
Pole at the ESR Zero.
5. Place 2
ND
Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier鈥檚 Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
20LOG
(V
IN
/鈭哣
OSC
)
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M
10M
FREQUENCY (Hz)
FIGURE 4. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Output Voltage Selection
The output voltage of the all the external voltage regulators
converter can be programmed to any level between their
individual input voltage and the internal reference, 0.8V. An
external resistor divider is used to scale the output voltage
relative to the reference voltage and feed it back to the
inverting input of the error amplifier, refer to the Typical
Application on page 3.
12
FN9142.4
February 8, 2005

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