CD74HC365, CD74HCT365, CD74HC366, CD74HCT366
Test Circuits and Waveforms
t
r
= 6ns
INPUT
90%
50%
10%
t
TLH
90%
50%
10%
t
PHL
t
PLH
t
f
= 6ns
V
CC
INPUT
GND
t
THL
t
r
= 6ns
2.7V
1.3V
0.3V
t
TLH
90%
INVERTING
OUTPUT
t
PHL
t
PLH
1.3V
10%
t
f
= 6ns
3V
GND
t
THL
INVERTING
OUTPUT
FIGURE 2. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
OUTPUT
DISABLE
90%
50%
10%
t
PZL
50%
10%
t
PHZ
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
90%
50%
OUTPUTS
DISABLED
OUTPUTS
ENABLED
t
PZH
6ns
V
CC
GND
FIGURE 3. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t
r
OUTPUT
DISABLE
6ns
t
f
2.7
1.3
t
PLZ
OUTPUT LOW
TO OFF
t
PHZ
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
90%
6ns
3V
0.3
t
PZL
GND
t
PLZ
OUTPUT LOW
TO OFF
10%
t
PZH
1.3V
1.3V
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 4. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 5. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
IC WITH
THREE-
STATE
OUTPUT
OUTPUT
R
L
= 1k鈩?/div>
C
L
50pF
V
CC
FOR t
PLZ
AND t
PZL
GND FOR t
PHZ
AND t
PZH
NOTE: Open drain waveforms t
PLZ
and t
PZL
are the same as those for three-state shown on the left. The test circuit is Output R
L
= 1k鈩?to
V
CC
, C
L
= 50pF.
FIGURE 6. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
7
                         
                        
                        prev
                        
                        next